bindings/pci/ti%2Cam65-pci-host.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   - Kishon Vijay Abraham I <kishon@ti.com>
14   - $ref: /schemas/pci/pci-host-bridge.yaml#
19       - ti,am654-pcie-rc
20       - ti,keystone-pcie
25   reg-names:
27       - const: app
28       - const: dbics
29       - const: config
30       - const: atu
35   power-domains:
38   ti,syscon-pcie-id:
39     $ref: /schemas/types.yaml#/definitions/phandle-array
41       - items:
42           - description: Phandle to the SYSCON entry
43           - description: pcie_device_id register offset within SYSCON
44     description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
46   ti,syscon-pcie-mode:
47     $ref: /schemas/types.yaml#/definitions/phandle-array
49       - items:
50           - description: Phandle to the SYSCON entry
51           - description: pcie_ctrl register offset within SYSCON
52     description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
54   msi-map: true
56   dma-coherent: true
58   num-viewport:
62     description: per-lane PHYs
66   phy-names:
70       pattern: '^pcie-phy[0-1]$'
73   - compatible
74   - reg
75   - reg-names
76   - max-link-speed
77   - ti,syscon-pcie-id
78   - ti,syscon-pcie-mode
79   - ranges
85         - ti,am654-pcie-rc
88     - dma-coherent
89     - power-domains
90     - msi-map
91     - num-viewport
96   - |
97     #include <dt-bindings/interrupt-controller/arm-gic.h>
98     #include <dt-bindings/interrupt-controller/irq.h>
99     #include <dt-bindings/phy/phy.h>
100     #include <dt-bindings/soc/ti,sci_pm_domain.h>
103         compatible = "ti,am654-pcie-rc";
108         reg-names = "app", "dbics", "config", "atu";
109         power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
110         #address-cells = <3>;
111         #size-cells = <2>;
114         ti,syscon-pcie-id = <&scm_conf 0x0210>;
115         ti,syscon-pcie-mode = <&scm_conf 0x4060>;
116         bus-range = <0x0 0xff>;
117         num-viewport = <16>;
118         max-link-speed = <2>;
119         dma-coherent;
121         msi-map = <0x0 &gic_its 0x0 0x10000>;
123         num-lanes = <1>;
125         phy-names = "pcie-phy0";