bindings/pci/starfive%2Cjh7110-pcie.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PCIe host controller
10   - Kevin Xie <kevin.xie@starfivetech.com>
13   - $ref: plda,xpressrich3-axi-common.yaml#
17     const: starfive,jh7110-pcie
21       - description: NOC bus clock
22       - description: Transport layer clock
23       - description: AXI MST0 clock
24       - description: APB clock
26   clock-names:
28       - const: noc
29       - const: tl
30       - const: axi_mst0
31       - const: apb
35       - description: AXI MST0 reset
36       - description: AXI SLAVE0 reset
37       - description: AXI SLAVE reset
38       - description: PCIE BRIDGE reset
39       - description: PCIE CORE reset
40       - description: PCIE APB reset
42   reset-names:
44       - const: mst0
45       - const: slv0
46       - const: slv
47       - const: brg
48       - const: core
49       - const: apb
51   starfive,stg-syscon:
52     $ref: /schemas/types.yaml#/definitions/phandle-array
56   perst-gpios:
62       Specified PHY is attached to PCIe controller.
66   - clocks
67   - resets
68   - starfive,stg-syscon
73   - |
74     #include <dt-bindings/gpio/gpio.h>
76         #address-cells = <2>;
77         #size-cells = <2>;
79         pcie@940000000 {
80             compatible = "starfive,jh7110-pcie";
83             reg-names = "cfg", "apb";
84             #address-cells = <3>;
85             #size-cells = <2>;
86             #interrupt-cells = <1>;
90             starfive,stg-syscon = <&stg_syscon>;
91             bus-range = <0x0 0xff>;
92             interrupt-parent = <&plic>;
94             interrupt-map-mask = <0x0 0x0 0x0 0x7>;
95             interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
99             msi-controller;
104             clock-names = "noc", "tl", "axi_mst0", "apb";
111             perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>;
114             pcie_intc0: interrupt-controller {
115                 #address-cells = <0>;
116                 #interrupt-cells = <1>;
117                 interrupt-controller;