Lines Matching +full:pcie +full:- +full:5
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
20 minItems: 5
22 - description: AHB clock for PCIe master
23 - description: AHB clock for PCIe slave
24 - description: AHB clock for PCIe dbi
25 - description: APB clock for PCIe
26 - description: Auxiliary clock for PCIe
27 - description: PIPE clock
28 - description: Reference clock for PCIe
30 clock-names:
31 minItems: 5
33 - const: aclk_mst
34 - const: aclk_slv
35 - const: aclk_dbi
36 - const: pclk
37 - const: aux
38 - const: pipe
39 - const: ref
42 minItems: 5
44 - description:
46 interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
49 - description:
51 interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
54 - description:
56 interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
58 - description:
60 interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc,
62 - description:
64 interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
67 - description:
69 - description:
71 - description:
73 - description:
76 interrupt-names:
77 minItems: 5
79 - const: sys
80 - const: pmc
81 - const: msg
82 - const: legacy
83 - const: err
84 - const: dma0
85 - const: dma1
86 - const: dma2
87 - const: dma3
89 num-lanes: true
94 phy-names:
95 const: pcie-phy
97 power-domains:
104 reset-names:
106 - const: pipe
107 - items:
108 - const: pwr
109 - const: pipe
112 - compatible
113 - reg
114 - reg-names
115 - clocks
116 - clock-names
117 - num-lanes
118 - phys
119 - phy-names
120 - power-domains
121 - resets
122 - reset-names