bindings/pci/qcom%2Cpcie-x1e80100.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Bjorn Andersson <andersson@kernel.org>
11   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19     const: qcom,pcie-x1e80100
25   reg-names:
27       - const: parf # Qualcomm specific registers
28       - const: dbi # DesignWare PCIe registers
29       - const: elbi # External local bus interface registers
30       - const: atu # ATU address space
31       - const: config # PCIe configuration space
32       - const: mhi # MHI registers
38   clock-names:
40       - const: aux # Auxiliary clock
41       - const: cfg # Configuration clock
42       - const: bus_master # Master AXI clock
43       - const: bus_slave # Slave AXI clock
44       - const: slave_q2a # Slave Q2A clock
45       - const: noc_aggr # Aggre NoC PCIe AXI clock
46       - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
52   interrupt-names:
54       - const: msi0
55       - const: msi1
56       - const: msi2
57       - const: msi3
58       - const: msi4
59       - const: msi5
60       - const: msi6
61       - const: msi7
67   reset-names:
70       - const: pci # PCIe core reset
71       - const: link_down # PCIe link down reset
74   - $ref: qcom,pcie-common.yaml#
79   - |
80     #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
81     #include <dt-bindings/gpio/gpio.h>
82     #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
83     #include <dt-bindings/interrupt-controller/arm-gic.h>
86         #address-cells = <2>;
87         #size-cells = <2>;
90             compatible = "qcom,pcie-x1e80100";
97             reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
101             bus-range = <0x00 0xff>;
103             linux,pci-domain = <0>;
104             num-lanes = <2>;
106             #address-cells = <3>;
107             #size-cells = <2>;
116             clock-names = "aux",
124             dma-coherent;
134             interrupt-names = "msi0", "msi1", "msi2", "msi3",
136             #interrupt-cells = <1>;
137             interrupt-map-mask = <0 0 0 0x7>;
138             interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
145             interconnect-names = "pcie-mem", "cpu-pcie";
147             iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
151             phy-names = "pciephy";
153             pinctrl-0 = <&pcie0_default_state>;
154             pinctrl-names = "default";
156             power-domains = <&gcc GCC_PCIE_4_GDSC>;
159             reset-names = "pci";
161             perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
162             wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;