bindings/pci/qcom%2Cpcie-sc8180x.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Bjorn Andersson <andersson@kernel.org>
11   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14   Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
15   DesignWare PCIe IP.
19     const: qcom,pcie-sc8180x
22     minItems: 5
25   reg-names:
26     minItems: 5
28       - const: parf # Qualcomm specific registers
29       - const: dbi # DesignWare PCIe registers
30       - const: elbi # External local bus interface registers
31       - const: atu # ATU address space
32       - const: config # PCIe configuration space
33       - const: mhi # MHI registers
39   clock-names:
41       - const: pipe # PIPE clock
42       - const: aux # Auxiliary clock
43       - const: cfg # Configuration clock
44       - const: bus_master # Master AXI clock
45       - const: bus_slave # Slave AXI clock
46       - const: slave_q2a # Slave Q2A clock
47       - const: ref # REFERENCE clock
48       - const: tbu # PCIe TBU clock
54   interrupt-names:
56       - const: msi0
57       - const: msi1
58       - const: msi2
59       - const: msi3
60       - const: msi4
61       - const: msi5
62       - const: msi6
63       - const: msi7
68   reset-names:
70       - const: pci
73   - $ref: qcom,pcie-common.yaml#
78   - |
79     #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
80     #include <dt-bindings/interconnect/qcom,sc8180x.h>
81     #include <dt-bindings/interrupt-controller/arm-gic.h>
84         #address-cells = <2>;
85         #size-cells = <2>;
87         pcie@1c00000 {
88             compatible = "qcom,pcie-sc8180x";
94             reg-names = "parf",
102             bus-range = <0x00 0xff>;
104             linux,pci-domain = <0>;
105             num-lanes = <2>;
107             #address-cells = <3>;
108             #size-cells = <2>;
110             assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
111             assigned-clock-rates = <19200000>;
121             clock-names = "pipe",
130             dma-coherent;
140             interrupt-names = "msi0",
148             #interrupt-cells = <1>;
149             interrupt-map-mask = <0 0 0 0x7>;
150             interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
157             interconnect-names = "pcie-mem", "cpu-pcie";
159             iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
163             phy-names = "pciephy";
165             power-domains = <&gcc PCIE_0_GDSC>;
168             reset-names = "pci";