Lines Matching +full:0 +full:x2800
78 reg = <0x0 0xf4000000 0x0 0x1000>,
79 <0x0 0xff3fe000 0x0 0x1000>,
80 <0x0 0xf3f20000 0x0 0x40000>,
81 <0x0 0xf5000000 0x0 0x2000>;
83 bus-range = <0x0 0xff>;
87 ranges = <0x02000000 0x0 0x00000000
88 0x0 0xf6000000
89 0x0 0x02000000>;
92 interrupts = <0 283 4>;
94 interrupt-map-mask = <0xf800 0 0 7>;
95 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
96 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
97 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
98 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
110 reg = <0x0 0xf4000000 0x0 0x1000000>,
111 <0x0 0xfc180000 0x0 0x1000>,
112 <0x0 0xf5000000 0x0 0x2000>;
114 bus-range = <0x0 0xff>;
119 ranges = <0x02000000 0x0 0x00000000
120 0x0 0xf6000000
121 0x0 0x02000000>;
126 interrupt-map-mask = <0 0 0 7>;
127 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
128 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
129 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
130 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
131 reset-gpios = <&gpio7 0 0>;
132 hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>;
133 pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
134 reg = <0 0 0 0 0>;
141 pcie@0,0 { // Lane 0: upstream
142 reg = <0 0 0 0 0>;
149 pcie@1,0 { // Lane 4: M.2
150 reg = <0x0800 0 0 0 0>;
153 reset-gpios = <&gpio3 1 0>;
159 pcie@5,0 { // Lane 5: Mini PCIe
160 reg = <0x2800 0 0 0 0>;
163 reset-gpios = <&gpio27 4 0 >;
169 pcie@7,0 { // Lane 6: Ethernet
170 reg = <0x03800 0 0 0 0>;
173 reset-gpios = <&gpio25 2 0 >;