bindings/pci/fsl%2Clayerscape-pcie-ep.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape PCIe Endpoint(EP) controller
10   - Frank Li <Frank.Li@nxp.com>
13   This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.
16   which is used to describe the PLL settings at the time of chip-reset.
19   register available in the Freescale PCIe controller register set,
20   which can allow determining the underlying DesignWare PCIe controller version
26       - fsl,ls2088a-pcie-ep
27       - fsl,ls1088a-pcie-ep
28       - fsl,ls1046a-pcie-ep
29       - fsl,ls1028a-pcie-ep
30       - fsl,lx2160ar2-pcie-ep
35   reg-names:
37       - const: regs
38       - const: addr_space
40   fsl,pcie-scfg:
43       physical PCIe controller index starting from '0'. This is used to get
46   big-endian:
48     description: If the PEX_LUT and PF register block is in big-endian, specify
51   dma-coherent: true
57   interrupt-names:
62   - compatible
63   - reg
64   - reg-names
67   - if:
71             - fsl,ls1028a-pcie-ep
72             - fsl,ls1046a-pcie-ep
73             - fsl,ls1088a-pcie-ep
76         interrupt-names:
78             - const: pme
83   - |
84     #include <dt-bindings/interrupt-controller/arm-gic.h>
87       #address-cells = <2>;
88       #size-cells = <2>;
90       pcie_ep1: pcie-ep@3400000 {
91         compatible = "fsl,ls1028a-pcie-ep";
94         reg-names = "regs", "addr_space";
96         interrupt-names = "pme";
97         num-ib-windows = <6>;
98         num-ob-windows = <8>;