Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Matthew Gerlach <matthew.gerlach@linux.intel.com>
16 - altr,pcie-root-port-1.0
17 - altr,pcie-root-port-2.0
21 - description: TX slave port region
22 - description: Control register access region
23 - description: Hard IP region
26 reg-names:
28 - const: Txs
29 - const: Cra
30 - const: Hip
36 interrupt-controller: true
38 interrupt-map-mask:
40 - const: 0
41 - const: 0
42 - const: 0
43 - const: 7
45 interrupt-map:
48 "#interrupt-cells":
51 msi-parent: true
54 - compatible
55 - reg
56 - reg-names
57 - interrupts
58 - "#interrupt-cells"
59 - interrupt-controller
60 - interrupt-map
61 - interrupt-map-mask
64 - $ref: /schemas/pci/pci-host-bridge.yaml#
65 - if:
69 - altr,pcie-root-port-1.0
75 reg-names:
83 reg-names:
90 - |
91 #include <dt-bindings/interrupt-controller/arm-gic.h>
92 #include <dt-bindings/interrupt-controller/irq.h>
94 compatible = "altr,pcie-root-port-1.0";
97 reg-names = "Txs", "Cra";
98 interrupt-parent = <&hps_0_arm_gic_0>;
100 interrupt-controller;
101 #interrupt-cells = <1>;
102 bus-range = <0x0 0xff>;
104 msi-parent = <&msi_to_gic_gen_0>;
105 #address-cells = <3>;
106 #size-cells = <2>;
107 interrupt-map-mask = <0 0 0 7>;
108 interrupt-map = <0 0 0 1 &pcie_0 0 0 0 1>,