bindings/net/stm32-dwmac.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   - Alexandre Torgue <alexandre.torgue@foss.st.com>
12   - Christophe Roullier <christophe.roullier@foss.st.com>
23           - st,stm32-dwmac
24           - st,stm32mp1-dwmac
25           - st,stm32mp13-dwmac
26           - st,stm32mp25-dwmac
28     - compatible
33       - items:
34           - enum:
35               - st,stm32mp25-dwmac
36           - const: snps,dwmac-5.20
37       - items:
38           - enum:
39               - st,stm32mp1-dwmac
40               - st,stm32mp13-dwmac
41           - const: snps,dwmac-4.20a
42       - items:
43           - enum:
44               - st,stm32-dwmac
45           - const: snps,dwmac-4.10a
46       - items:
47           - enum:
48               - st,stm32-dwmac
49           - const: snps,dwmac-3.50a
53   reg-names:
55       - const: stmmaceth
60       - description: GMAC main clock
61       - description: MAC TX clock
62       - description: MAC RX clock
63       - description: For MPU family, used for power mode
64       - description: For MPU family, used for PHY without quartz
65       - description: PTP clock
67   clock-names:
72         - stmmaceth
73         - mac-clk-tx
74         - mac-clk-rx
75         - ethstp
76         - eth-ck
77         - ptp_ref
79   st,syscon:
80     $ref: /schemas/types.yaml#/definitions/phandle-array
82       - minItems: 2
84           - description: phandle to the syscon node which encompases the glue register
85           - description: offset of the control register
86           - description: field to set mask in register
88       Should be phandle/offset pair. The phandle to the syscon node which
92   st,ext-phyclk:
99   st,eth-clk-sel:
104   st,eth-ref-clk-sel:
110   access-controllers:
115   - compatible
116   - clocks
117   - clock-names
118   - st,syscon
123   - $ref: snps,dwmac.yaml#
124   - if:
129               - st,stm32-dwmac
130               - st,stm32mp1-dwmac
131               - st,stm32mp25-dwmac
134         st,syscon:
139   - if:
144               - st,stm32mp13-dwmac
147         st,syscon:
153   - |
154     #include <dt-bindings/interrupt-controller/arm-gic.h>
155     #include <dt-bindings/clock/stm32mp1-clks.h>
158            compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
160            reg-names = "stmmaceth";
162            interrupt-names = "macirq";
163            clock-names = "stmmaceth",
164                      "mac-clk-tx",
165                      "mac-clk-rx",
167                      "eth-ck";
173            st,syscon = <&syscfg 0x4>;
175            snps,axi-config = <&stmmac_axi_config_0>;
177            phy-mode = "rgmii";
180   - |
183            compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
185            reg-names = "stmmaceth";
187            interrupt-names = "macirq", "eth_wake_irq";
188            clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
190            st,syscon = <&syscfg 0x4>;
192            snps,mixed-burst;
193            phy-mode = "mii";
196   - |
199            compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
201            reg-names = "stmmaceth";
203            interrupt-names = "macirq";
204            clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
206            st,syscon = <&syscfg 0x4>;
208            phy-mode = "mii";