bindings/net/qcom%2Cipq4019-mdio.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm IPQ40xx MDIO Controller
10   - Robert Marko <robert.marko@sartura.hr>
15       - enum:
16           - qcom,ipq4019-mdio
17           - qcom,ipq5018-mdio
19       - items:
20           - enum:
21               - qcom,ipq6018-mdio
22               - qcom,ipq8074-mdio
23               - qcom,ipq9574-mdio
24           - const: qcom,ipq4019-mdio
26   "#address-cells":
29   "#size-cells":
30     const: 0
36       the first Address and length of the register set for the MDIO controller.
42       - description: MDIO clock source frequency fixed to 100MHZ
44   clock-names:
46       - const: gcc_mdio_ahb_clk
48   clock-frequency:
50       The MDIO bus clock that must be output by the MDIO bus hardware, if
64   - compatible
65   - reg
66   - "#address-cells"
67   - "#size-cells"
70   - $ref: mdio.yaml#
72   - if:
77               - qcom,ipq5018-mdio
78               - qcom,ipq6018-mdio
79               - qcom,ipq8074-mdio
80               - qcom,ipq9574-mdio
83         - clocks
84         - clock-names
88         clock-names: false
93   - |
94     mdio@90000 {
95       #address-cells = <1>;
96       #size-cells = <0>;
97       compatible = "qcom,ipq4019-mdio";
98       reg = <0x90000 0x64>;
100       ethphy0: ethernet-phy@0 {
101         reg = <0>;
104       ethphy1: ethernet-phy@1 {
108       ethphy2: ethernet-phy@2 {
112       ethphy3: ethernet-phy@3 {
116       ethphy4: ethernet-phy@4 {