bindings/net/qcom%2Cethqos.yaml

1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Bhupesh Sharma <bhupesh.sharma@linaro.org>
17   - $ref: snps,dwmac.yaml#
22       - qcom,qcs404-ethqos
23       - qcom,sa8775p-ethqos
24       - qcom,sc8280xp-ethqos
25       - qcom,sm8150-ethqos
30   reg-names:
32       - const: stmmaceth
33       - const: rgmii
38       - description: Combined signal for various interrupt events
39       - description: The interrupt that occurs when Rx exits the LPI state
40       - description: The interrupt that occurs when HW safety error triggered
42   interrupt-names:
45       - const: macirq
46       - enum: [eth_lpi, sfty]
47       - const: sfty
52   clock-names:
54       - const: stmmaceth
55       - const: pclk
56       - const: ptp_ref
57       - enum:
58           - rgmii
59           - phyaux
64   dma-coherent: true
68   phy-names:
72   - compatible
73   - clocks
74   - clock-names
75   - reg-names
80   - |
81     #include <dt-bindings/interrupt-controller/arm-gic.h>
82     #include <dt-bindings/clock/qcom,gcc-qcs404.h>
83     #include <dt-bindings/gpio/gpio.h>
86       compatible = "qcom,qcs404-ethqos";
89       reg-names = "stmmaceth", "rgmii";
90       clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
98       interrupt-names = "macirq", "eth_lpi", "sfty";
100       rx-fifo-depth = <4096>;
101       tx-fifo-depth = <4096>;
104       snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
105       snps,reset-active-low;
106       snps,reset-delays-us = <0 10000 10000>;
108       pinctrl-names = "default";
109       pinctrl-0 = <&ethernet_defaults>;
111       phy-handle = <&phy1>;
112       phy-mode = "rgmii";
114         #address-cells = <0x1>;
115         #size-cells = <0x0>;
117         compatible = "snps,dwmac-mdio";
119           compatible = "ethernet-phy-ieee802.3-c22";
120           device_type = "ethernet-phy";
123           #phy-cells = <0>;