bindings/net/motorcomm%2Cyt8xxx.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Frank Sae <frank.sae@motor-comm.com>
13   - $ref: ethernet-phy.yaml#
18       - ethernet-phy-id4f51.e91a
19       - ethernet-phy-id4f51.e91b
21   rx-internal-delay-ps:
24       internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30   tx-internal-delay-ps:
33       internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
38   motorcomm,clk-out-frequency-hz:
43   motorcomm,keep-pll-enabled:
49   motorcomm,auto-sleep-disabled:
55   motorcomm,rx-clk-drv-microamp:
58       The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
59       be configured with hardware pull-up resistors to match the SOC voltage
60       (usually 1.8V).
61       The software can read the registers to obtain the LDO voltage and configure
65       |   1.8v  | 1200 2100 2700 2910 3110 3600 3970 4350 |
66       |   3.3v  | 3070 4080 4370 4680 5020 5450 5740 6140 |
72   motorcomm,rx-data-drv-microamp:
75       The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
76       be configured with hardware pull-up resistors to match the SOC voltage
77       (usually 1.8V).
78       The software can read the registers to obtain the LDO voltage and configure
82       |   1.8v  | 1200 2100 2700 2910 3110 3600 3970 4350 |
83       |   3.3v  | 3070 4080 4370 4680 5020 5450 5740 6140 |
89   motorcomm,tx-clk-adj-enabled:
92       Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk.
95   motorcomm,tx-clk-10-inverted:
101   motorcomm,tx-clk-100-inverted:
107   motorcomm,tx-clk-1000-inverted:
116   - |
118         #address-cells = <1>;
119         #size-cells = <0>;
120         phy-mode = "rgmii-id";
121         ethernet-phy@4 {
125             compatible = "ethernet-phy-id4f51.e91a";
128             rx-internal-delay-ps = <2100>;
129             tx-internal-delay-ps = <150>;
130             motorcomm,clk-out-frequency-hz = <0>;
131             motorcomm,keep-pll-enabled;
132             motorcomm,auto-sleep-disabled;
135   - |
137         #address-cells = <1>;
138         #size-cells = <0>;
139         phy-mode = "rgmii";
140         ethernet-phy@5 {
144             compatible = "ethernet-phy-id4f51.e91a";
147             motorcomm,clk-out-frequency-hz = <125000000>;
148             motorcomm,keep-pll-enabled;
149             motorcomm,auto-sleep-disabled;