bindings/net/mdio-mux-gpio.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Andrew Lunn <andrew@lunn.ch>
17   - $ref: /schemas/net/mdio-mux.yaml#
21     const: mdio-mux-gpio
30   - compatible
31   - gpios
36   - |
38      An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
42     mdio-mux {
43         compatible = "mdio-mux-gpio";
45         mdio-parent-bus = <&smi1>;
46         #address-cells = <1>;
47         #size-cells = <0>;
51             #address-cells = <1>;
52             #size-cells = <0>;
54             ethernet-phy@1 {
56                 marvell,reg-init = <3 0x10 0 0x5777>,
60                 interrupt-parent = <&gpio>;
61                 interrupts = <10 8>; /* Pin 10, active low */
63             ethernet-phy@2 {
65                 marvell,reg-init = <3 0x10 0 0x5777>,
69                 interrupt-parent = <&gpio>;
70                 interrupts = <10 8>; /* Pin 10, active low */
72             ethernet-phy@3 {
74                 marvell,reg-init = <3 0x10 0 0x5777>,
78                 interrupt-parent = <&gpio>;
79                 interrupts = <10 8>; /* Pin 10, active low */
81             ethernet-phy@4 {
83                 marvell,reg-init = <3 0x10 0 0x5777>,
87                 interrupt-parent = <&gpio>;
88                 interrupts = <10 8>; /* Pin 10, active low */
94             #address-cells = <1>;
95             #size-cells = <0>;
97             ethernet-phy@1 {
99                 marvell,reg-init = <3 0x10 0 0x5777>,
103                 interrupt-parent = <&gpio>;
104                 interrupts = <12 8>; /* Pin 12, active low */
106             ethernet-phy@2 {
108                 marvell,reg-init = <3 0x10 0 0x5777>,
112                 interrupt-parent = <&gpio>;
113                 interrupts = <12 8>; /* Pin 12, active low */
115             ethernet-phy@3 {
117                 marvell,reg-init = <3 0x10 0 0x5777>,
121                 interrupt-parent = <&gpio>;
122                 interrupts = <12 8>; /* Pin 12, active low */
124             ethernet-phy@4 {
126                 marvell,reg-init = <3 0x10 0 0x5777>,
130                 interrupt-parent = <&gpio>;
131                 interrupts = <12 8>; /* Pin 12, active low */