Lines Matching +full:mdio +full:- +full:bus
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Frame Manager MDIO Device
10 - Frank Li <Frank.Li@nxp.com>
12 description: FMan MDIO Node.
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
19 - fsl,fman-xmdio
20 - fsl,fman-memac-mdio
22 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
23 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
24 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
32 - description: A reference to the input clock of the controller
38 fsl,fman-internal-mdio:
41 Fman has internal MDIO for internal PCS(Physical
42 Coding Sublayer) PHYs and external MDIO for external PHYs.
44 MDIO are different. Must be included for internal MDIO.
46 fsl,erratum-a009885:
52 MDIO read operation.
54 fsl,erratum-a011043:
59 set when reading internal PCS registers. MDIO reads to
64 PCS registers through MDIO. As a workaround, all internal
65 MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
67 For internal PHY device on internal mdio bus, a PHY node should be created.
68 See the definition of the PHY node in booting-without-of.txt for an
70 - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
71 - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
75 little-endian:
78 IP block is little-endian mode. The default endian mode is big-endian.
81 - compatible
82 - reg
85 - $ref: mdio.yaml#
90 - |
91 mdio@f1000 {
92 compatible = "fsl,fman-xmdio";
97 - |
98 mdio@e3120 {
99 compatible = "fsl,fman-mdio";
101 fsl,fman-internal-mdio;
102 #address-cells = <1>;
103 #size-cells = <0>;
105 tbi-phy@8 {
107 device_type = "tbi-phy";
111 - |
112 mdio@f1000 {
113 compatible = "fsl,fman-memac-mdio";
115 fsl,fman-internal-mdio;
116 #address-cells = <1>;
117 #size-cells = <0>;
119 pcsphy6: ethernet-phy@0 {