bindings/net/ethernet-phy.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Andrew Lunn <andrew@lunn.ch>
11   - Florian Fainelli <f.fainelli@gmail.com>
12   - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21       pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24     - $nodename
28     pattern: "^ethernet-phy(@[a-f0-9]+)?$"
32       - const: ethernet-phy-ieee802.3-c22
34       - const: ethernet-phy-ieee802.3-c45
36       - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
46       - items:
47           - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
48           - const: ethernet-phy-ieee802.3-c22
49       - items:
50           - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
51           - const: ethernet-phy-ieee802.3-c45
62   max-speed:
64       - 10
65       - 100
66       - 1000
67       - 2500
68       - 5000
69       - 10000
70       - 20000
71       - 25000
72       - 40000
73       - 50000
74       - 56000
75       - 100000
76       - 200000
80   phy-10base-t1l-2.4vpp:
89   broken-turn-around:
96   brr-mode:
100       defined in the BroadR-Reach link mode specification under 1BR-100 and
101       1BR-10 names. The PHY must be configured to operate in BroadR-Reach mode
108       that the PHY uses a fixed crystal or an internal oscillator.
110   enet-phy-lane-swap:
113       If set, indicates the PHY will swap the TX/RX lanes to
117   enet-phy-lane-no-swap:
121       TX/RX lanes. This property allows the PHY to work correctly after
125   eee-broken-100tx:
131   eee-broken-1000t:
137   eee-broken-10gt:
143   eee-broken-1000kx:
149   eee-broken-10gkx4:
155   eee-broken-10gkr:
162     $ref: /schemas/types.yaml#/definitions/phandle-array
167   phy-is-integrated:
179   reset-names:
182   reset-gpios:
187   reset-assert-us:
189       Delay after the reset was asserted in microseconds. If this
190       property is missing the delay will be skipped.
192   reset-deassert-us:
194       Delay after the reset was deasserted in microseconds. If
195       this property is missing the delay will be skipped.
202   rx-internal-delay-ps:
204       RGMII Receive PHY Clock Delay defined in pico seconds.  This is used for
205       PHY's that have configurable RX internal delays.  If this property is
206       present then the PHY applies the RX delay.
208   tx-internal-delay-ps:
210       RGMII Transmit PHY Clock Delay defined in pico seconds.  This is used for
211       PHY's that have configurable TX internal delays. If this property is
212       present then the PHY applies the TX delay.
218       '#address-cells':
221       '#size-cells':
225       '^led@[a-f0-9]+$':
237           - reg
244   - reg
249   - |
250     #include <dt-bindings/leds/common.h>
253         #address-cells = <1>;
254         #size-cells = <0>;
256         ethernet-phy@0 {
257             compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
258             interrupt-parent = <&PIC>;
263             reset-names = "phy";
264             reset-gpios = <&gpio1 4 1>;
265             reset-assert-us = <1000>;
266             reset-deassert-us = <2000>;
269                 #address-cells = <1>;
270                 #size-cells = <0>;
276                     default-state = "keep";