bindings/net/ethernet-phy.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Common Properties
10   - Andrew Lunn <andrew@lunn.ch>
11   - Florian Fainelli <f.fainelli@gmail.com>
12   - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21       pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24     - $nodename
28     pattern: "^ethernet-phy(@[a-f0-9]+)?$"
32       - const: ethernet-phy-ieee802.3-c22
34       - const: ethernet-phy-ieee802.3-c45
36       - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
38           If the PHY reports an incorrect ID (or none at all) then the
39           compatible list may contain an entry with the correct PHY ID
41           The first group of digits is the 16 bit Phy Identifier 1
43           second group of digits is the Phy Identifier 2 register,
46       - items:
47           - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
48           - const: ethernet-phy-ieee802.3-c22
49       - items:
50           - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
51           - const: ethernet-phy-ieee802.3-c45
57       The ID number for the PHY.
62   max-speed:
64       - 10
65       - 100
66       - 1000
67       - 2500
68       - 5000
69       - 10000
70       - 20000
71       - 25000
72       - 40000
73       - 50000
74       - 56000
75       - 100000
76       - 200000
78       Maximum PHY supported speed in Mbits / seconds.
80   phy-10base-t1l-2.4vpp:
89   broken-turn-around:
92       If set, indicates the PHY device does not correctly release
96   brr-mode:
100       defined in the BroadR-Reach link mode specification under 1BR-100 and
101       1BR-10 names. The PHY must be configured to operate in BroadR-Reach mode
107       External clock connected to the PHY. If not specified it is assumed
108       that the PHY uses a fixed crystal or an internal oscillator.
110   enet-phy-lane-swap:
113       If set, indicates the PHY will swap the TX/RX lanes to
117   enet-phy-lane-no-swap:
120       If set, indicates that PHY will disable swap of the
121       TX/RX lanes. This property allows the PHY to work correctly after
125   eee-broken-100tx:
128       Mark the corresponding energy efficient ethernet mode as
129       broken and request the ethernet to stop advertising it.
131   eee-broken-1000t:
134       Mark the corresponding energy efficient ethernet mode as
135       broken and request the ethernet to stop advertising it.
137   eee-broken-10gt:
140       Mark the corresponding energy efficient ethernet mode as
141       broken and request the ethernet to stop advertising it.
143   eee-broken-1000kx:
146       Mark the corresponding energy efficient ethernet mode as
147       broken and request the ethernet to stop advertising it.
149   eee-broken-10gkx4:
152       Mark the corresponding energy efficient ethernet mode as
153       broken and request the ethernet to stop advertising it.
155   eee-broken-10gkr:
158       Mark the corresponding energy efficient ethernet mode as
159       broken and request the ethernet to stop advertising it.
162     $ref: /schemas/types.yaml#/definitions/phandle-array
167   phy-is-integrated:
170       If set, indicates that the PHY is integrated into the same
171       physical package as the Ethernet MAC. If needed, muxers
172       should be configured to ensure the integrated PHY is
174       should be configured so that the external PHY is used.
179   reset-names:
180     const: phy
182   reset-gpios:
185       The GPIO phandle and specifier for the PHY reset signal.
187   reset-assert-us:
192   reset-deassert-us:
202   rx-internal-delay-ps:
204       RGMII Receive PHY Clock Delay defined in pico seconds.  This is used for
205       PHY's that have configurable RX internal delays.  If this property is
206       present then the PHY applies the RX delay.
208   tx-internal-delay-ps:
210       RGMII Transmit PHY Clock Delay defined in pico seconds.  This is used for
211       PHY's that have configurable TX internal delays. If this property is
212       present then the PHY applies the TX delay.
218       '#address-cells':
221       '#size-cells':
225       '^led@[a-f0-9]+$':
232               This define the LED index in the PHY or the MAC. It's really
237           - reg
244   - reg
249   - |
250     #include <dt-bindings/leds/common.h>
252     ethernet {
253         #address-cells = <1>;
254         #size-cells = <0>;
256         ethernet-phy@0 {
257             compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
258             interrupt-parent = <&PIC>;
263             reset-names = "phy";
264             reset-gpios = <&gpio1 4 1>;
265             reset-assert-us = <1000>;
266             reset-deassert-us = <2000>;
269                 #address-cells = <1>;
270                 #size-cells = <0>;
276                     default-state = "keep";