Lines Matching +full:mdio +full:- +full:pin
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
14 since at least 2008. The switch has one pin ADDR4 that controls the
15 MDIO address of the switch to be 0x10 or 0x00, and on the MDIO bus
17 independent devices on address 0x00-0x04 or 0x10-0x14, so in difference
19 MDIO bus for the PHY devices.
31 reset-gpios:
37 - $ref: dsa.yaml#/$defs/ethernet-ports
40 - compatible
41 - reg
46 - |
47 #include <dt-bindings/gpio/gpio.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 mdio {
50 #address-cells = <1>;
51 #size-cells = <0>;
53 ethernet-switch@16 {
57 ethernet-ports {
58 #address-cells = <1>;
59 #size-cells = <0>;
61 ethernet-port@0 {
65 ethernet-port@1 {
69 ethernet-port@2 {
73 ethernet-port@3 {
77 ethernet-port@5 {
79 phy-mode = "rev-mii";
81 fixed-link {
83 full-duplex;