bindings/net/cortina%2Cgemini-ethernet.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini Ethernet Controller
10   - Linus Walleij <linus.walleij@linaro.org>
13   This ethernet controller is found in the Gemini SoC family:
19     const: cortina,gemini-ethernet
23     description: must contain the global registers and the V-bit and A-bit
26   "#address-cells":
29   "#size-cells":
34 # The subnodes represents the two ethernet ports in this device.
38   "^ethernet-port@[0-9]+$":
41     description: contains the resources for ethernet port
43       - $ref: ethernet-controller.yaml#
46         const: cortina,gemini-ethernet-port
50           - description: DMA/TOE memory
51           - description: GMAC memory area of the port
55         description: should contain the interrupt line of the port.
60         description: this must provide an SoC-integrated reset line for the port.
65                      clocking the silicon in this port
67       clock-names:
71       - reg
72       - compatible
73       - interrupts
74       - resets
75       - clocks
76       - clock-names
79   - compatible
80   - reg
81   - ranges
86   - |
87     #include <dt-bindings/interrupt-controller/irq.h>
88     #include <dt-bindings/clock/cortina,gemini-clock.h>
89     #include <dt-bindings/reset/cortina,gemini-reset.h>
91       #address-cells = <1>;
92       #size-cells = <0>;
93       phy0: ethernet-phy@1 {
95         device_type = "ethernet-phy";
97       phy1: ethernet-phy@3 {
99         device_type = "ethernet-phy";
104     ethernet@60000000 {
105         compatible = "cortina,gemini-ethernet";
107               <0x60004000 0x2000>, /* V-bit */
108               <0x60006000 0x2000>; /* A-bit */
109         #address-cells = <1>;
110         #size-cells = <1>;
113         gmac0: ethernet-port@0 {
114                 compatible = "cortina,gemini-ethernet-port";
115                 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
116                       <0x6000a000 0x2000>; /* Port 0 GMAC */
117                 interrupt-parent = <&intcon>;
121                 clock-names = "PCLK";
122                 phy-mode = "rgmii";
123                 phy-handle = <&phy0>;
126         gmac1: ethernet-port@1 {
127                 compatible = "cortina,gemini-ethernet-port";
128                 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
129                       <0x6000e000 0x2000>; /* Port 1 GMAC */
130                 interrupt-parent = <&intcon>;
134                 clock-names = "PCLK";
135                 phy-mode = "rgmii";
136                 phy-handle = <&phy1>;