Lines Matching +full:magic +full:- +full:packet
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
22 - enum:
23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC
24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
25 - const: cdns,gem # Generic
28 - items:
29 - enum:
30 - xlnx,versal-gem # Xilinx Versal
31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
33 - const: cdns,gem # Generic
35 - items:
36 - enum:
37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
38 - cdns,sam9x60-macb # Microchip sam9x60 SoC
39 - microchip,mpfs-macb # Microchip PolarFire SoC
40 - const: cdns,macb # Generic
42 - items:
43 - enum:
44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs
45 - enum:
46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
47 - const: cdns,macb # Generic
49 - enum:
50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs
51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs
52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs
53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs
54 - cdns,np4-macb # NP4 SoC devices
55 - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface
56 - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC
58 - cdns,emac # Generic
59 - cdns,gem # Generic
60 - cdns,macb # Generic
62 - items:
63 - enum:
64 - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface
65 - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
70 - description: Basic register set
71 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
82 clock-names:
85 - enum: [ ether_clk, hclk, pclk ]
86 - enum: [ hclk, pclk ]
87 - const: tx_clk
88 - enum: [ rx_clk, tsu_clk ]
89 - const: tsu_clk
91 local-mac-address: true
93 phy-mode: true
95 phy-handle: true
104 controller instance with zynqmp-reset driver.
106 reset-names:
109 fixed-link: true
114 power-domains:
117 cdns,rx-watermark:
121 the receiver will only begin to forward the packet to the external
122 AHB or AXI slave when enough packet data is stored in the SRAM packet buffer.
123 rx-watermark corresponds to the number of SRAM buffer locations,
127 '#address-cells':
130 '#size-cells':
140 "^ethernet-phy@[0-9a-f]$":
142 $ref: ethernet-phy.yaml#
145 reset-gpios: true
147 magic-packet:
151 Indicates that the hardware supports waking up via magic packet.
156 - compatible
157 - reg
158 - interrupts
159 - clocks
160 - clock-names
161 - phy-mode
164 - $ref: ethernet-controller.yaml#
166 - if:
171 const: sifive,fu540-c000-gem
180 - |
185 cdns,rx-watermark = <0x44>;
186 phy-mode = "rmii";
187 local-mac-address = [3a 0e 03 04 05 06];
188 clock-names = "pclk", "hclk", "tx_clk";
190 #address-cells = <1>;
191 #size-cells = <0>;
193 ethernet-phy@1 {
195 reset-gpios = <&pioE 6 1>;
199 - |
200 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
201 #include <dt-bindings/power/xlnx-zynqmp-power.h>
202 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
203 #include <dt-bindings/phy/phy.h>
206 #address-cells = <2>;
207 #size-cells = <2>;
209 compatible = "xlnx,zynqmp-gem", "cdns,gem";
210 interrupt-parent = <&gic>;
216 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
217 #address-cells = <1>;
218 #size-cells = <0>;
220 power-domains = <&zynqmp_firmware PD_ETH_1>;
222 reset-names = "gem1_rst";
223 phy-mode = "sgmii";
225 fixed-link {
227 full-duplex;