bindings/mtd/ti%2Cgpmc-nand.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Tony Lindgren <tony@atomide.com>
11   - Roger Quadros <rogerq@kernel.org>
20       - enum:
21           - ti,am64-nand
22           - ti,omap2-nand
29       - description: Interrupt for fifoevent
30       - description: Interrupt for termcount
32   "#address-cells": true
34   "#size-cells": true
36   ti,nand-ecc-opt:
41   ti,nand-xfer-type:
44     enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]
45     default: prefetch-polled
47   ti,elm-id:
52   nand-bus-width:
54       Bus width to the NAND chip
59   rb-gpios:
61       GPIO connection to R/B signal from NAND chip
65   - $ref: /schemas/memory-controllers/ti,gpmc-child.yaml
66   - $ref: mtd.yaml#
69   - compatible
70   - reg
71   - ti,nand-ecc-opt
76   - |
77     #include <dt-bindings/interrupt-controller/arm-gic.h>
78     #include <dt-bindings/gpio/gpio.h>
80     gpmc: memory-controller@50000000 {
81       compatible = "ti,am3352-gpmc";
83       dma-names = "rxtx";
85       clock-names = "fck";
88       gpmc,num-cs = <7>;
89       gpmc,num-waitpins = <2>;
90       #address-cells = <2>;
91       #size-cells = <1>;
92       interrupt-controller;
93       #interrupt-cells = <2>;
94       gpio-controller;
95       #gpio-cells = <2>;
99         compatible = "ti,omap2-nand";
101         interrupt-parent = <&gpmc>;
104         ti,nand-xfer-type = "prefetch-dma";
105         ti,nand-ecc-opt = "bch16";
106         ti,elm-id = <&elm>;
107         #address-cells = <1>;
108         #size-cells = <1>;
111         nand-bus-width = <8>;
112         rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;  /* gpmc_wait0 */
115         gpmc,device-width = <1>;