bindings/mtd/nxp-spifi.txt

1 * NXP SPI Flash Interface (SPIFI)
3 NXP SPIFI is a specialized SPI interface for serial Flash devices.
4 It supports one Flash device with 1-, 2- and 4-bits width in SPI
5 mode 0 or 3. The controller operates in either command or memory
6 mode. In memory mode the Flash is accessible from the CPU as
10   - compatible : Should be "nxp,lpc1773-spifi"
11   - reg : the first contains the register location and length,
13   - reg-names: Should contain the reg names "spifi" and "flash"
14   - interrupts : Should contain the interrupt for the device
15   - clocks : The clocks needed by the SPIFI controller
16   - clock-names : Should contain the clock names "spifi" and "reg"
19  - resets : phandle + reset specifier
21 The SPI Flash must be a child of the SPIFI node and must have a
22 compatible property as specified in bindings/mtd/jedec,spi-nor.txt
25  - spi-cpol : Controller only supports mode 0 and 3 so either
26               both spi-cpol and spi-cpha should be present or
28  - spi-cpha : See above
29  - spi-rx-bus-width : Used to select how many pins that are used
32 See bindings/spi/spi-bus.txt for more information.
36 	compatible = "nxp,lpc1773-spifi";
38 	reg-names = "spifi", "flash";
41 	clock-names = "spifi", "reg";
44 	flash@0 {
45 		compatible = "jedec,spi-nor";
46 		spi-cpol;
47 		spi-cpha;
48 		spi-rx-bus-width = <4>;
49 		#address-cells = <1>;
50 		#size-cells = <1>;