Lines Matching +full:nand +full:- +full:ecc +full:- +full:engine
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
18 is paired with a custom DMA engine (inventively named "Flash DMA") which
27 -- Additional SoC-specific NAND controller properties --
29 The NAND controller is integrated differently on the variety of SoCs on which
31 bits with which to control the 8 exposed NAND interrupts, as well as hardware
35 interesting ways, sometimes with registers that lump multiple NAND-related
39 register resources within the NAND controller node above.
44 - items:
45 - enum:
46 - brcm,brcmnand-v2.1
47 - brcm,brcmnand-v2.2
48 - brcm,brcmnand-v4.0
49 - brcm,brcmnand-v5.0
50 - brcm,brcmnand-v6.0
51 - brcm,brcmnand-v6.1
52 - brcm,brcmnand-v6.2
53 - brcm,brcmnand-v7.0
54 - brcm,brcmnand-v7.1
55 - brcm,brcmnand-v7.2
56 - brcm,brcmnand-v7.3
57 - const: brcm,brcmnand
58 - description: BCMBCA SoC-specific NAND controller
60 - const: brcm,nand-bcm63138
61 - enum:
62 - brcm,brcmnand-v7.0
63 - brcm,brcmnand-v7.1
64 - const: brcm,brcmnand
65 - description: iProc SoC-specific NAND controller
67 - const: brcm,nand-iproc
68 - const: brcm,brcmnand-v6.1
69 - const: brcm,brcmnand
70 - description: BCM63168 SoC-specific NAND controller
72 - const: brcm,nand-bcm63168
73 - const: brcm,nand-bcm6368
74 - const: brcm,brcmnand-v4.0
75 - const: brcm,brcmnand
81 reg-names:
85 enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ]
90 - description: NAND CTLRDY interrupt
91 … - description: FLASH_DMA_DONE (if flash DMA is available) or FLASH_EDU_DONE (if EDU is available)
93 interrupt-names:
96 - const: nand_ctlrdy
97 - enum:
98 - flash_dma_done
99 - flash_edu_done
103 description: reference to the clock for the NAND controller
105 clock-names:
106 const: nand
108 brcm,nand-has-wp:
110 Some versions of this IP include a write-protect
116 brcm,wp-not-connected:
118 Use this property when WP pin is not physically wired to the NAND chip.
124 "^nand@[a-f0-9]$":
126 $ref: raw-nand-chip.yaml
131 nand-ecc-step-size:
134 brcm,nand-oob-sector-size:
137 expected for the ECC layout in use. This size, in
138 addition to the strength and step-size,
139 determines how the hardware BCH engine will lay
142 the flash geometry (particularly the NAND page
144 from NAND, the boot controller has only a limited
145 number of available options for its default ECC
149 brcm,nand-ecc-use-strap:
151 This property requires the host system to get the ECC related
152 settings from the SoC NAND boot strap configuration instead of
153 the generic NAND ECC settings. This is a common hardware design
154 on BCMBCA based boards. This strap ECC option and generic NAND
155 ECC option can not be specified at the same time.
161 - $ref: nand-controller.yaml#
162 - if:
166 const: brcm,nand-bcm63138
169 reg-names:
171 - const: nand
172 - const: nand-int-base
173 - if:
177 const: brcm,nand-bcm6368
180 reg-names:
182 - const: nand
183 - const: nand-int-base
184 - const: nand-cache
185 - if:
189 const: brcm,nand-iproc
192 reg-names:
194 - const: nand
195 - const: iproc-idm
196 - const: iproc-ext
197 - if:
199 - interrupts
205 - interrupt-names
207 - if:
209 "^nand@[a-f0-9]$":
211 - brcm,nand-ecc-use-strap
214 "^nand@[a-f0-9]$":
216 nand-ecc-strength: false
217 nand-ecc-step-size: false
218 nand-ecc-maximize: false
219 nand-ecc-algo: false
220 brcm,nand-oob-sector-size: false
225 - reg
226 - reg-names
229 - |
230 nand-controller@f0442800 {
231 compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
234 reg-names = "nand", "flash-dma";
235 interrupt-parent = <&hif_intr2_intc>;
237 interrupt-names = "nand_ctlrdy", "flash_dma_done";
239 #address-cells = <1>;
240 #size-cells = <0>;
242 nand@1 {
245 nand-on-flash-bbt;
246 nand-ecc-strength = <12>;
247 nand-ecc-step-size = <512>;
249 #address-cells = <1>;
250 #size-cells = <1>;
253 - |
254 nand-controller@10000200 {
255 compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
256 "brcm,brcmnand-v4.0", "brcm,brcmnand";
260 reg-names = "nand", "nand-int-base", "nand-cache";
261 interrupt-parent = <&periph_intc>;
264 clock-names = "nand";
266 #address-cells = <1>;
267 #size-cells = <0>;
269 nand@0 {
272 nand-on-flash-bbt;
273 nand-ecc-strength = <1>;
274 nand-ecc-step-size = <512>;
276 #address-cells = <1>;
277 #size-cells = <1>;