bindings/mmc/samsung%2Cexynos-dw-mshc.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12   - Jaehoon Chung <jh80.chung@samsung.com>
13   - Krzysztof Kozlowski <krzk@kernel.org>
18       - enum:
19           - axis,artpec8-dw-mshc
20           - samsung,exynos4210-dw-mshc
21           - samsung,exynos4412-dw-mshc
22           - samsung,exynos5250-dw-mshc
23           - samsung,exynos5420-dw-mshc
24           - samsung,exynos5420-dw-mshc-smu
25           - samsung,exynos7-dw-mshc
26           - samsung,exynos7-dw-mshc-smu
27       - items:
28           - enum:
29               - samsung,exynos5433-dw-mshc-smu
30               - samsung,exynos7885-dw-mshc-smu
31               - samsung,exynos850-dw-mshc-smu
32           - const: samsung,exynos7-dw-mshc-smu
46   clock-names:
48       - const: biu
49       - const: ciu
51   samsung,dw-mshc-ciu-div:
58   samsung,dw-mshc-ddr-timing:
59     $ref: /schemas/types.yaml#/definitions/uint32-array
61       - description: CIU clock phase shift value for tx mode
64       - description: CIU clock phase shift value for rx mode
68       The value of CUI clock phase shift value in transmit mode and CIU clock
69       phase shift value in receive mode for double data rate mode operation.
70       See also samsung,dw-mshc-hs400-timing property.
72   samsung,dw-mshc-hs400-timing:
73     $ref: /schemas/types.yaml#/definitions/uint32-array
75       - description: CIU clock phase shift value for tx mode
78       - description: CIU clock phase shift value for rx mode
82       The value of CIU TX and RX clock phase shift value for HS400 mode
85         - valid value for tx phase shift and rx phase shift is 0 to 7.
86         - when CIU clock divider value is set to 3, all possible 8 phase shift
88         - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
89           phase shift clocks should be 0.
90       If missing, values from samsung,dw-mshc-ddr-timing property are used.
92   samsung,dw-mshc-sdr-timing:
93     $ref: /schemas/types.yaml#/definitions/uint32-array
95       - description: CIU clock phase shift value for tx mode
98       - description: CIU clock phase shift value for rx mode
102       The value of CIU clock phase shift value in transmit mode and CIU clock
103       phase shift value in receive mode for single data rate mode operation.
104       See also samsung,dw-mshc-hs400-timing property.
106   samsung,read-strobe-delay:
113   - compatible
114   - reg
115   - interrupts
116   - clocks
117   - clock-names
118   - samsung,dw-mshc-ddr-timing
119   - samsung,dw-mshc-sdr-timing
122   - $ref: synopsys-dw-mshc-common.yaml#
123   - if:
128               - samsung,exynos5250-dw-mshc
129               - samsung,exynos5420-dw-mshc
130               - samsung,exynos7-dw-mshc
131               - samsung,exynos7-dw-mshc-smu
132               - axis,artpec8-dw-mshc
135         - samsung,dw-mshc-ciu-div
140   - |
141     #include <dt-bindings/clock/exynos5420.h>
142     #include <dt-bindings/interrupt-controller/arm-gic.h>
145         compatible = "samsung,exynos5420-dw-mshc";
147         #address-cells = <1>;
148         #size-cells = <0>;
151         clock-names = "biu", "ciu";
152         fifo-depth = <0x40>;
153         card-detect-delay = <200>;
154         samsung,dw-mshc-ciu-div = <3>;
155         samsung,dw-mshc-sdr-timing = <0 4>;
156         samsung,dw-mshc-ddr-timing = <0 2>;
157         pinctrl-names = "default";
158         pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
159         bus-width = <4>;
160         cap-sd-highspeed;
161         max-frequency = <200000000>;
162         vmmc-supply = <&ldo19_reg>;
163         vqmmc-supply = <&ldo13_reg>;
164         sd-uhs-sdr50;
165         sd-uhs-sdr104;
166         sd-uhs-ddr50;