Lines Matching +full:tuning +full:- +full:step
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
20 - mediatek,mt6795-mmc
21 - mediatek,mt7620-mmc
22 - mediatek,mt7622-mmc
23 - mediatek,mt7986-mmc
24 - mediatek,mt8135-mmc
25 - mediatek,mt8173-mmc
26 - mediatek,mt8183-mmc
27 - mediatek,mt8516-mmc
28 - items:
29 - const: mediatek,mt7623-mmc
30 - const: mediatek,mt2701-mmc
31 - items:
32 - enum:
33 - mediatek,mt8186-mmc
34 - mediatek,mt8188-mmc
35 - mediatek,mt8192-mmc
36 - mediatek,mt8195-mmc
37 - mediatek,mt8365-mmc
38 - const: mediatek,mt8183-mmc
43 - description: base register (required).
44 - description: top base register (required for MT8183).
52 clock-names:
58 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
63 interrupt-names:
65 - const: msdc
66 - const: sdio_wakeup
68 pinctrl-names:
70 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
75 - const: default
76 - const: state_uhs
77 - const: state_eint
79 pinctrl-0:
84 pinctrl-1:
89 pinctrl-2:
94 hs400-ds-delay:
101 mediatek,hs200-cmd-int-delay:
110 mediatek,hs400-cmd-int-delay:
119 mediatek,hs400-cmd-resp-sel-rising:
126 mediatek,hs400-ds-dly3:
131 For different corner IC, the time is different about one step, it is
138 mediatek,latch-ck:
141 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
144 applied to compatible "mediatek,mt2701-mmc".
148 mediatek,tuning-step:
151 Some SoCs need extend tuning step for better delay value to avoid CRC issue.
152 If not present, default tuning step is 32. For eMMC and SD, this can yield
160 reset-names:
164 - compatible
165 - reg
166 - interrupts
167 - clocks
168 - clock-names
169 - pinctrl-names
170 - pinctrl-0
171 - pinctrl-1
172 - vmmc-supply
173 - vqmmc-supply
176 - $ref: mmc-controller.yaml#
177 - if:
181 - mediatek,mt2701-mmc
182 - mediatek,mt6779-mmc
183 - mediatek,mt6795-mmc
184 - mediatek,mt7620-mmc
185 - mediatek,mt7622-mmc
186 - mediatek,mt7623-mmc
187 - mediatek,mt8135-mmc
188 - mediatek,mt8173-mmc
189 - mediatek,mt8183-mmc
190 - mediatek,mt8186-mmc
191 - mediatek,mt8188-mmc
192 - mediatek,mt8195-mmc
193 - mediatek,mt8516-mmc
199 - description: source clock
200 - description: HCLK which used for host
201 - description: independent source clock gate
202 clock-names:
205 - const: source
206 - const: hclk
207 - const: source_cg
209 - if:
213 const: mediatek,mt2712-mmc
219 - description: source clock
220 - description: HCLK which used for host
221 - description: independent source clock gate
222 - description: bus clock used for internal register access (required for MSDC0/3).
223 clock-names:
226 - const: source
227 - const: hclk
228 - const: source_cg
229 - const: bus_clk
231 - if:
235 const: mediatek,mt8183-mmc
241 - if:
246 - mediatek,mt7986-mmc
252 - description: source clock
253 - description: HCLK which used for host
254 - description: independent source clock gate
255 - description: bus clock used for internal register access (required for MSDC0/3).
256 - description: msdc subsys clock gate
257 clock-names:
260 - const: source
261 - const: hclk
262 - const: source_cg
263 - const: bus_clk
264 - const: sys_cg
266 - if:
270 - mediatek,mt8186-mmc
271 - mediatek,mt8188-mmc
272 - mediatek,mt8195-mmc
277 - description: source clock
278 - description: HCLK which used for host
279 - description: independent source clock gate
280 - description: crypto clock used for data encrypt/decrypt (optional)
281 clock-names:
283 - const: source
284 - const: hclk
285 - const: source_cg
286 - const: crypto
288 - if:
292 const: mediatek,mt8192-mmc
297 - description: source clock
298 - description: HCLK which used for host
299 - description: independent source clock gate
300 - description: msdc subsys clock gate
301 - description: peripheral bus clock gate
302 - description: AXI bus clock gate
303 - description: AHB bus clock gate
304 clock-names:
306 - const: source
307 - const: hclk
308 - const: source_cg
309 - const: sys_cg
310 - const: pclk_cg
311 - const: axi_cg
312 - const: ahb_cg
317 - |
318 #include <dt-bindings/interrupt-controller/irq.h>
319 #include <dt-bindings/interrupt-controller/arm-gic.h>
320 #include <dt-bindings/clock/mt8173-clk.h>
322 compatible = "mediatek,mt8173-mmc";
325 vmmc-supply = <&mt6397_vemc_3v3_reg>;
326 vqmmc-supply = <&mt6397_vio18_reg>;
329 clock-names = "source", "hclk";
330 pinctrl-names = "default", "state_uhs";
331 pinctrl-0 = <&mmc0_pins_default>;
332 pinctrl-1 = <&mmc0_pins_uhs>;
333 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
334 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
335 hs400-ds-delay = <0x14015>;
336 mediatek,hs200-cmd-int-delay = <26>;
337 mediatek,hs400-cmd-int-delay = <14>;
338 mediatek,hs400-cmd-resp-sel-rising;
342 compatible = "mediatek,mt8173-mmc";
344 clock-names = "source", "hclk";
347 interrupt-names = "msdc", "sdio_wakeup";
348 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
350 pinctrl-names = "default", "state_uhs", "state_eint";
351 pinctrl-0 = <&mmc2_pins_default>;
352 pinctrl-1 = <&mmc2_pins_uhs>;
353 pinctrl-2 = <&mmc2_pins_eint>;
354 bus-width = <4>;
355 max-frequency = <200000000>;
356 cap-sd-highspeed;
357 sd-uhs-sdr104;
358 keep-power-in-suspend;
359 wakeup-source;
360 cap-sdio-irq;
361 no-mmc;
362 no-sd;
363 non-removable;
364 vmmc-supply = <&sdio_fixed_3v3>;
365 vqmmc-supply = <&mt6397_vgp3_reg>;
366 mmc-pwrseq = <&wifi_pwrseq>;