Lines Matching full:xenon

4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
7 title: Marvell Xenon SDHCI Controller
11   mmc-controller.yaml and the properties used by the Xenon implementation.
13   Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
37           - const: marvell,sdhci-xenon
44       for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
49       For other compatible strings, one register area for Xenon IP.
64   marvell,xenon-sdhc-id:
73   marvell,xenon-phy-type:
79       Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
80       marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
82       marvell,xenon-phy-type = "emmc 5.0 phy"
87       that this Xenon SDHC only supports eMMC 5.1.
89   marvell,xenon-phy-znr:
98   marvell,xenon-phy-zpr:
107   marvell,xenon-phy-nr-success-tun:
116   marvell,xenon-phy-tun-step-divider:
122   marvell,xenon-phy-slow-mode:
131   marvell,xenon-tun-count:
135       Xenon SDHC SoC usually doesn't provide re-tuning counter in
151             - description: Xenon IP registers
212       marvell,xenon-phy-slow-mode;
213       marvell,xenon-tun-count = <11>;
235       marvell,xenon-tun-count = <9>;
244       compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
268       compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";