Lines Matching +full:0 +full:xaa0000

66     minimum: 0
70       Operation Control Register Bit[7:0].  Set/clear the corresponding bit to
91     minimum: 0
92     maximum: 0x1f
93     default: 0xf
100     minimum: 0
101     maximum: 0x1f
102     default: 0xf
111     default: 0x4
133     default: 0x9
207       reg = <0xaa0000 0x1000>;
209       clocks = <&emmc_clk 0>, <&axi_clk 0>;
228       reg = <0xab0000 0x1000>;
232       clocks = <&sdclk 0>, <&axi_clk 0>;
245       reg = <0xaa0000 0x1000>,
246             <0x17808 0x4>;
248       clocks = <&emmcclk 0>;
269       reg = <0xab0000 0x1000>,
270             <0x17808 0x4>;
274       clocks = <&sdclk 0>;