Lines Matching +full:phase +full:- +full:locked

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Yang Xiwen <forbidden405@outlook.com>
15       - hisilicon,hi3798cv200-dw-mshc
16       - hisilicon,hi3798mv200-dw-mshc
26       - description: bus interface unit clock
27       - description: card interface unit clock
28       - description: card input sample phase clock
29       - description: controller output drive phase clock
31   clock-names:
33       - const: ciu
34       - const: biu
35       - const: ciu-sample
36       - const: ciu-drive
38   hisilicon,sap-dll-reg:
39     $ref: /schemas/types.yaml#/definitions/phandle-array
41       DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path.
44       - description: A phandle pointed to the CRG syscon node
45       - description: Sample DLL register offset in CRG address space
48   - compatible
49   - reg
50   - interrupts
51   - clocks
52   - clock-names
55   - $ref: synopsys-dw-mshc-common.yaml#
57   - if:
61             const: hisilicon,hi3798mv200-dw-mshc
64         - hisilicon,sap-dll-reg
67         hisilicon,sap-dll-reg: false
72   - |
73     #include <dt-bindings/clock/histb-clock.h>
74     #include <dt-bindings/interrupt-controller/arm-gic.h>
77         compatible = "hisilicon,hi3798cv200-dw-mshc";
84         clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
86         reset-names = "reset";
87         pinctrl-names = "default";
88         pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
90         fifo-depth = <256>;
91         clock-frequency = <200000000>;
92         cap-mmc-highspeed;
93         mmc-ddr-1_8v;
94         mmc-hs200-1_8v;
95         non-removable;
96         bus-width = <8>;