bindings/mmc/cdns%2Csdhci.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Masahiro Yamada <yamada.masahiro@socionext.com>
15       - enum:
16           - amd,pensando-elba-sd4hc
17           - microchip,mpfs-sd4hc
18           - socionext,uniphier-sd4hc
19       - const: cdns,sd4hc
34   # PHY DLL input delays:
39   cdns,phy-input-delay-sd-highspeed:
40     description: Value of the delay in the input path for SD high-speed timing
41     $ref: /schemas/types.yaml#/definitions/uint32
45   cdns,phy-input-delay-legacy:
47     $ref: /schemas/types.yaml#/definitions/uint32
51   cdns,phy-input-delay-sd-uhs-sdr12:
53     $ref: /schemas/types.yaml#/definitions/uint32
57   cdns,phy-input-delay-sd-uhs-sdr25:
59     $ref: /schemas/types.yaml#/definitions/uint32
63   cdns,phy-input-delay-sd-uhs-sdr50:
65     $ref: /schemas/types.yaml#/definitions/uint32
69   cdns,phy-input-delay-sd-uhs-ddr50:
71     $ref: /schemas/types.yaml#/definitions/uint32
75   cdns,phy-input-delay-mmc-highspeed:
76     description: Value of the delay in the input path for MMC high-speed timing
77     $ref: /schemas/types.yaml#/definitions/uint32
81   cdns,phy-input-delay-mmc-ddr:
82     description: Value of the delay in the input path for eMMC high-speed DDR timing
84   # PHY DLL clock delays:
88     $ref: /schemas/types.yaml#/definitions/uint32
92   cdns,phy-dll-delay-sdclk:
96     $ref: /schemas/types.yaml#/definitions/uint32
100   cdns,phy-dll-delay-sdclk-hsmmc:
104     $ref: /schemas/types.yaml#/definitions/uint32
108   cdns,phy-dll-delay-strobe:
112     $ref: /schemas/types.yaml#/definitions/uint32
117   - compatible
118   - reg
119   - interrupts
120   - clocks
123   - $ref: mmc-controller.yaml
124   - if:
128             const: amd,pensando-elba-sd4hc
133             - description: Host controller registers
134             - description: Elba byte-lane enable register for writes
136         - resets
145   - |
147         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
150         clocks = <&clk 4>;
151         bus-width = <8>;
152         mmc-ddr-1_8v;
153         mmc-hs200-1_8v;
154         mmc-hs400-1_8v;
155         cdns,phy-dll-delay-sdclk = <0>;