mips/img/xilfpga.txt

14 the ARTIX-7 FPGA by Xilinx.
18 - microAptiv UP core m14Kc
19 - 50MHz clock speed
20 - 128Mbyte DDR RAM	at 0x0000_0000
21 - 8Kbyte RAM		at 0x1000_0000
22 - axi_intc		at 0x1020_0000
23 - axi_uart16550		at 0x1040_0000
24 - axi_gpio		at 0x1060_0000
25 - axi_i2c		at 0x10A0_0000
26 - custom_gpio		at 0x10C0_0000
27 - axi_ethernetlite	at 0x10E0_0000
28 - 8Kbyte BootRAM	at 0x1FC0_0000
31 --------------------
32  - compatible: Must include "digilent,nexys4ddr","img,xilfpga".
35 ----------
37  - #address-cells: Must be 1.
38  - #size-cells: Must be 0.
39 A CPU sub-node is also required for at least CPU 0. Required properties:
40  - device_type: Must be "cpu".
41  - compatible: Must be "mips,m14Kc".
42  - reg: Must be <0>.
43  - clocks: phandle to ext clock for fixed-clock received by MIPS core.
47 	compatible = "img,xilfpga","digilent,nexys4ddr";
49 		#address-cells = <1>;
50 		#size-cells = <0>;
54 			compatible = "mips,m14Kc";
61 		compatible = "fixed-clock";
62 		#clock-cells = <0>;
63 		clock-frequency = <50000000>;
67 --------------
69 The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
82 At this point, the board is ready to load the Linux kernel