bindings/memory-controllers/xlnx%2Czynqmp-ocmc-1.0.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynqmp OCM(On-Chip Memory) Controller
10   - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11   - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
14   The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
15   and recover from a single-bit memory fault.On a write, if all bytes are
17   the write-data that is written into the data RAM. If one or more bytes are
23     const: xlnx,zynqmp-ocmc-1.0
26     maxItems: 1
29     maxItems: 1
32   - compatible
33   - reg
34   - interrupts
39   - |
40     #include <dt-bindings/interrupt-controller/arm-gic.h>
41     memory-controller@ff960000 {
42       compatible = "xlnx,zynqmp-ocmc-1.0";