bindings/memory-controllers/xlnx%2Czynq-ddrc-a05.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Krzysztof Kozlowski <krzk@kernel.org>
11   - Michal Simek <michal.simek@amd.com>
14   The Zynq DDR ECC controller has an optional ECC support in half-bus width
15   (16-bit) configuration. It is capable of correcting single bit ECC errors
20     const: xlnx,zynq-ddrc-a05
26   - compatible
27   - reg
32   - |
33     memory-controller@f8006000 {
34       compatible = "xlnx,zynq-ddrc-a05";