bindings/memory-controllers/rockchip%2Crk3399-dmc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Brian Norris <briannorris@chromium.org>
15       - rockchip,rk3399-dmc
17   devfreq-events:
18     $ref: /schemas/types.yaml#/definitions/phandle
26   clock-names:
28       - const: dmc_clk
30   operating-points-v2: true
32   center-supply:
37     $ref: /schemas/types.yaml#/definitions/phandle
49     $ref: /schemas/types.yaml#/definitions/uint32
51       For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
52       DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
58     $ref: /schemas/types.yaml#/definitions/uint32
60       Configure the PD_IDLE value. Defines the power-down idle period in which
61       memories are placed into power-down mode if bus is idle for PD_IDLE DFI
62       clock cycles.
63       See also rockchip,pd-idle-ns.
67     $ref: /schemas/types.yaml#/definitions/uint32
69       Configure the SR_IDLE value. Defines the self-refresh idle period in
70       which memories are placed into self-refresh mode if bus is idle for
71       SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
72       See also rockchip,sr-idle-ns.
77     $ref: /schemas/types.yaml#/definitions/uint32
79       Defines the memory self-refresh and controller clock gating idle period.
80       Memories are placed into self-refresh mode and memory controller clock
81       arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
83       See also rockchip,sr-mc-gate-idle-ns.
87     $ref: /schemas/types.yaml#/definitions/uint32
89       Defines the self-refresh power down idle period in which memories are
90       placed into self-refresh power down mode if bus is idle for
91       srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
93       See also rockchip,srpd-lite-idle-ns.
97     $ref: /schemas/types.yaml#/definitions/uint32
99       Defines the standby idle period in which memories are placed into
100       self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
101       if bus is idle for standby_idle * DFI clock cycles.
102       See also rockchip,standby-idle-ns.
106     $ref: /schemas/types.yaml#/definitions/uint32
114     $ref: /schemas/types.yaml#/definitions/uint32
122     $ref: /schemas/types.yaml#/definitions/uint32
127     $ref: /schemas/types.yaml#/definitions/uint32
136     $ref: /schemas/types.yaml#/definitions/uint32
144     $ref: /schemas/types.yaml#/definitions/uint32
152     $ref: /schemas/types.yaml#/definitions/uint32
155       (including command line, address line and clock line) drive strength.
160     $ref: /schemas/types.yaml#/definitions/uint32
168     $ref: /schemas/types.yaml#/definitions/uint32
175     $ref: /schemas/types.yaml#/definitions/uint32
184     $ref: /schemas/types.yaml#/definitions/uint32
192     $ref: /schemas/types.yaml#/definitions/uint32
200     $ref: /schemas/types.yaml#/definitions/uint32
203       (including command line, address line and clock line) drive strength.
208     $ref: /schemas/types.yaml#/definitions/uint32
216     $ref: /schemas/types.yaml#/definitions/uint32
222     $ref: /schemas/types.yaml#/definitions/uint32
231     $ref: /schemas/types.yaml#/definitions/uint32
239     $ref: /schemas/types.yaml#/definitions/uint32
247     $ref: /schemas/types.yaml#/definitions/uint32
255     $ref: /schemas/types.yaml#/definitions/uint32
263     $ref: /schemas/types.yaml#/definitions/uint32
265       When the DRAM type is LPDDR4, this parameter defines the PHY side clock
271     $ref: /schemas/types.yaml#/definitions/uint32
279     $ref: /schemas/types.yaml#/definitions/uint32
285   rockchip,pd-idle-ns:
287       Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
288       period in which memories are placed into power-down mode if bus is idle
291   rockchip,sr-idle-ns:
293       Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
294       period in which memories are placed into self-refresh mode if bus is idle
298   rockchip,sr-mc-gate-idle-ns:
300       Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
301       Memories are placed into self-refresh mode and memory controller clock
304   rockchip,srpd-lite-idle-ns:
306       Defines the self-refresh power down idle period in which memories are
307       placed into self-refresh power down mode if bus is idle for
310   rockchip,standby-idle-ns:
312       Defines the standby idle period in which memories are placed into
313       self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
316   rockchip,pd-idle-dis-freq-hz:
318       Defines the power-down idle disable frequency in Hz. When the DDR
319       frequency is greater than pd-idle-dis-freq, power-down idle is disabled.
320       See also rockchip,pd-idle-ns.
322   rockchip,sr-idle-dis-freq-hz:
324       Defines the self-refresh idle disable frequency in Hz. When the DDR
325       frequency is greater than sr-idle-dis-freq, self-refresh idle is
326       disabled. See also rockchip,sr-idle-ns.
328   rockchip,sr-mc-gate-idle-dis-freq-hz:
330       Defines the self-refresh and memory-controller clock gating disable
332       sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
333       rockchip,sr-mc-gate-idle-ns.
335   rockchip,srpd-lite-idle-dis-freq-hz:
337       Defines the self-refresh power down idle disable frequency in Hz. When
338       the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will
339       not be placed into self-refresh power down mode when idle. See also
340       rockchip,srpd-lite-idle-ns.
342   rockchip,standby-idle-dis-freq-hz:
345       is greater than standby-idle-dis-freq, standby idle is disabled. See also
346       rockchip,standby-idle-ns.
349   - compatible
350   - devfreq-events
351   - clocks
352   - clock-names
353   - operating-points-v2
354   - center-supply
359   - |
360     #include <dt-bindings/clock/rk3399-cru.h>
361     #include <dt-bindings/interrupt-controller/arm-gic.h>
362     memory-controller {
363       compatible = "rockchip,rk3399-dmc";
364       devfreq-events = <&dfi>;
368       clock-names = "dmc_clk";
369       operating-points-v2 = <&dmc_opp_table>;
370       center-supply = <&ppvar_centerlogic>;
371       rockchip,pd-idle-ns = <160>;
372       rockchip,sr-idle-ns = <10240>;
373       rockchip,sr-mc-gate-idle-ns = <40960>;
374       rockchip,srpd-lite-idle-ns = <61440>;
375       rockchip,standby-idle-ns = <81920>;
379       rockchip,pd-idle-dis-freq-hz = <1000000000>;
380       rockchip,sr-idle-dis-freq-hz = <1000000000>;
381       rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
382       rockchip,srpd-lite-idle-dis-freq-hz = <0>;
383       rockchip,standby-idle-dis-freq-hz = <928000000>;