bindings/memory-controllers/rockchip%2Crk3399-dmc.yaml

44       The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
108       Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116       Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
130       When the DRAM type is DDR3, this parameter defines the ODT disable
131       frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
138       When the DRAM type is DDR3, this parameter defines the DRAM side drive
146       When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154       When the DRAM type is DDR3, this parameter defines the phy side CA line
162       When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170       When the DRAM type is DDR3, this parameter defines the PHY side ODT
178       When the DRAM type is LPDDR3, this parameter defines then ODT disable
179       frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
186       When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
194       When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
202       When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
210       When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
218       When dram type is LPDDR3, this parameter define the phy side odt
225       When the DRAM type is LPDDR4, this parameter defines the ODT disable
226       frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
233       When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
241       When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
249       When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
257       When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
265       When the DRAM type is LPDDR4, this parameter defines the PHY side clock
273       When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
281       When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
318       Defines the power-down idle disable frequency in Hz. When the DDR
324       Defines the self-refresh idle disable frequency in Hz. When the DDR
331       frequency in Hz. When the DDR frequency is greater than
332       sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
337       Defines the self-refresh power down idle disable frequency in Hz. When
339       not be placed into self-refresh power down mode when idle. See also
344       Defines the standby idle disable frequency in Hz. When the DDR frequency