bindings/memory-controllers/rockchip%2Crk3399-dmc.yaml

60       Configure the PD_IDLE value. Defines the power-down idle period in which
69       Configure the SR_IDLE value. Defines the self-refresh idle period in
79       Defines the memory self-refresh and controller clock gating idle period.
89       Defines the self-refresh power down idle period in which memories are
99       Defines the standby idle period in which memories are placed into
108       Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116       Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
124       Defines the auto PD disable frequency in MHz.
130       When the DRAM type is DDR3, this parameter defines the ODT disable
138       When the DRAM type is DDR3, this parameter defines the DRAM side drive
146       When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154       When the DRAM type is DDR3, this parameter defines the phy side CA line
162       When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170       When the DRAM type is DDR3, this parameter defines the PHY side ODT
178       When the DRAM type is LPDDR3, this parameter defines then ODT disable
186       When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
194       When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
202       When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
210       When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
225       When the DRAM type is LPDDR4, this parameter defines the ODT disable
233       When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
241       When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
249       When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
257       When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
265       When the DRAM type is LPDDR4, this parameter defines the PHY side clock
273       When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
281       When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
287       Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
293       Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
300       Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
306       Defines the self-refresh power down idle period in which memories are
312       Defines the standby idle period in which memories are placed into
318       Defines the power-down idle disable frequency in Hz. When the DDR
324       Defines the self-refresh idle disable frequency in Hz. When the DDR
330       Defines the self-refresh and memory-controller clock gating disable
337       Defines the self-refresh power down idle disable frequency in Hz. When
344       Defines the standby idle disable frequency in Hz. When the DDR frequency