bindings/memory-controllers/nvidia%2Ctegra20-mc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC Memory Controller
10   - Dmitry Osipenko <digetx@gmail.com>
11   - Jon Hunter <jonathanh@nvidia.com>
12   - Thierry Reding <thierry.reding@gmail.com>
15   The Tegra20 Memory Controller merges request streams from various client
18   has a configurable arbitration algorithm to allow the user to fine-tune
21   Tegra20 Memory Controller includes the GART (Graphics Address Relocation
27     const: nvidia,tegra20-mc-gart
31       - description: controller registers
32       - description: GART registers
37   clock-names:
39       - const: mc
44   "#reset-cells":
47   "#iommu-cells":
50   "#interconnect-cells":
54   - compatible
55   - reg
56   - interrupts
57   - clocks
58   - clock-names
59   - "#reset-cells"
60   - "#iommu-cells"
61   - "#interconnect-cells"
66   - |
67     memory-controller@7000f000 {
68         compatible = "nvidia,tegra20-mc-gart";
70               <0x58000000 0x02000000>;	/* GART aperture */
72         clock-names = "mc";
76         #iommu-cells = <0>;
77         #reset-cells = <1>;
78         #interconnect-cells = <1>;