Lines Matching +full:external +full:- +full:memory +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
19 Up to 15 GiB of physical memory can be supported. Security features such as
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
32 - nvidia,tegra186-mc
33 - nvidia,tegra194-mc
34 - nvidia,tegra234-mc
40 reg-names:
46 - description: MC general interrupt
48 "#address-cells":
51 "#size-cells":
56 dma-ranges: true
58 "#interconnect-cells":
62 "^external-memory-controller@[0-9a-f]+$":
64 The bulk of the work involved in controlling the external memory
65 controller on NVIDIA Tegra186 and later is performed on the BPMP. This
67 which the external memory is clocked and a remote procedure call that
73 - enum:
74 - nvidia,tegra186-emc
75 - nvidia,tegra194-emc
76 - nvidia,tegra234-emc
84 - description: EMC general interrupt
88 - description: external memory clock
90 clock-names:
92 - const: emc
94 "#interconnect-cells":
103 - if:
106 const: nvidia,tegra186-emc
112 - if:
115 const: nvidia,tegra194-emc
121 - if:
124 const: nvidia,tegra234-emc
133 - compatible
134 - reg
135 - interrupts
136 - clocks
137 - clock-names
138 - "#interconnect-cells"
139 - nvidia,bpmp
142 - if:
145 const: nvidia,tegra186-mc
150 description: 5 memory controller channels and 1 for stream-id registers
152 reg-names:
154 - const: sid
155 - const: broadcast
156 - const: ch0
157 - const: ch1
158 - const: ch2
159 - const: ch3
161 - if:
164 const: nvidia,tegra194-mc
169 description: 17 memory controller channels and 1 for stream-id registers
171 reg-names:
173 - const: sid
174 - const: broadcast
175 - const: ch0
176 - const: ch1
177 - const: ch2
178 - const: ch3
179 - const: ch4
180 - const: ch5
181 - const: ch6
182 - const: ch7
183 - const: ch8
184 - const: ch9
185 - const: ch10
186 - const: ch11
187 - const: ch12
188 - const: ch13
189 - const: ch14
190 - const: ch15
192 - if:
195 const: nvidia,tegra234-mc
200 description: 17 memory controller channels and 1 for stream-id registers
202 reg-names:
204 - const: sid
205 - const: broadcast
206 - const: ch0
207 - const: ch1
208 - const: ch2
209 - const: ch3
210 - const: ch4
211 - const: ch5
212 - const: ch6
213 - const: ch7
214 - const: ch8
215 - const: ch9
216 - const: ch10
217 - const: ch11
218 - const: ch12
219 - const: ch13
220 - const: ch14
221 - const: ch15
226 - compatible
227 - reg
228 - reg-names
229 - interrupts
230 - "#address-cells"
231 - "#size-cells"
234 - |
235 #include <dt-bindings/clock/tegra186-clock.h>
236 #include <dt-bindings/interrupt-controller/arm-gic.h>
239 #address-cells = <2>;
240 #size-cells = <2>;
242 memory-controller@2c00000 {
243 compatible = "nvidia,tegra186-mc";
244 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
250 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
253 #address-cells = <2>;
254 #size-cells = <2>;
259 * Memory clients have access to all 40 bits that the memory
260 * controller can address.
262 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
264 external-memory-controller@2c60000 {
265 compatible = "nvidia,tegra186-emc";
269 clock-names = "emc";
271 #interconnect-cells = <0>;