bindings/memory-controllers/exynos-srom.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Krzysztof Kozlowski <krzk@kernel.org>
13   The SROM controller can be used to attach external peripherals. In this case
19       - const: samsung,exynos4210-srom
24   "#address-cells":
27   "#size-cells":
35       <bank-number> 0 <parent address of bank> <size>
39   "^.*@[0-3],[a-f0-9]+$":
56       reg-io-width:
61       samsung,srom-page-mode:
67       samsung,srom-timing:
68         $ref: /schemas/types.yaml#/definitions/uint32-array
77           Tacp: Page mode access cycle at Page mode (0 - 15)
78           Tcah: Address holding time after CSn (0 - 15)
79           Tcoh: Chip selection hold on OEn (0 - 15)
80           Tacc: Access cycle (0 - 31, the actual time is N + 1)
81           Tcos: Chip selection set-up before OEn (0 - 15)
82           Tacs: Address set-up before CSn (0 - 15)
85       - reg
86       - samsung,srom-timing
89   - compatible
90   - reg
95   - |
97     memory-controller@12560000 {
98         compatible = "samsung,exynos4210-srom";
102   - |
104     memory-controller@12570000 {
105         #address-cells = <2>;
106         #size-cells = <1>;
112         compatible = "samsung,exynos4210-srom";
118             phy-mode = "mii";
119             interrupt-parent = <&gpx0>;
121             reg-io-width = <2>;
122             smsc,irq-push-pull;
123             smsc,force-internal-phy;
125             samsung,srom-page-mode;
126             samsung,srom-timing = <9 12 1 9 1 1>;