memory-controllers/ddr/jedec%2Clpddr3.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10   - Krzysztof Kozlowski <krzk@kernel.org>
13   - $ref: jedec,lpddr-props.yaml#
18       - items:
19           - enum:
20               - samsung,K3QF2F20DB
21           - const: jedec,lpddr3
22       - items:
23           - pattern: "^lpddr3-[0-9a-f]{2},[0-9a-f]{4}$"
24           - const: jedec,lpddr3
26   '#address-cells':
30   manufacturer-id:
37   '#size-cells':
41   tCKE-min-tck:
48   tCKESR-min-tck:
55   tDQSCK-min-tck:
62   tFAW-min-tck:
66       Four-bank activate window in terms of number of clock cycles.
68   tMRD-min-tck:
74   tR2R-C2C-min-tck:
78       Additional READ-to-READ delay in chip-to-chip cases in terms of number
81   tRAS-min-tck:
87   tRC-min-tck:
91       ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
93   tRCD-min-tck:
97       RAS-to-CAS delay in terms of number of clock cycles.
99   tRFC-min-tck:
105   tRL-min-tck:
111   tRPab-min-tck:
117   tRPpb-min-tck:
123   tRRD-min-tck:
129   tRTP-min-tck:
136   tW2W-C2C-min-tck:
140       Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
143   tWL-min-tck:
149   tWR-min-tck:
155   tWTR-min-tck:
159       Internal WRITE-to-READ command delay in terms of number of clock cycles.
161   tXP-min-tck:
165       Exit power-down to next valid command delay in terms of number of clock
168   tXSR-min-tck:
176   "^timings((-[0-9])+|(@[0-9a-f]+))?$":
177     $ref: jedec,lpddr3-timings.yaml
181       speed-bin. The user may provide the timings for as many speed-bins as is
185   - compatible
186   - density
187   - io-width
192   - |
196         io-width = <32>;
198         tCKE-min-tck = <2>;
199         tCKESR-min-tck = <2>;
200         tDQSCK-min-tck = <5>;
201         tFAW-min-tck = <5>;
202         tMRD-min-tck = <5>;
203         tR2R-C2C-min-tck = <0>;
204         tRAS-min-tck = <5>;
205         tRC-min-tck = <6>;
206         tRCD-min-tck = <3>;
207         tRFC-min-tck = <17>;
208         tRL-min-tck = <14>;
209         tRPab-min-tck = <2>;
210         tRPpb-min-tck = <2>;
211         tRRD-min-tck = <2>;
212         tRTP-min-tck = <2>;
213         tW2W-C2C-min-tck = <0>;
214         tWL-min-tck = <8>;
215         tWR-min-tck = <7>;
216         tWTR-min-tck = <2>;
217         tXP-min-tck = <2>;
218         tXSR-min-tck = <12>;
221             compatible = "jedec,lpddr3-timings";
222             max-freq = <800000000>;
223             min-freq = <100000000>;
228             tR2R-C2C = <0>;
237             tW2W-C2C = <0>;
241             tXSR = <70000>;