memory-controllers/ddr/jedec%2Clpddr3-timings.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10   - Krzysztof Kozlowski <krzk@kernel.org>
14     const: jedec,lpddr3-timings
19       Maximum DDR clock frequency for the speed-bin, in Hz.
20       Property is deprecated, use max-freq.
23   max-freq:
26       Maximum DDR clock frequency for the speed-bin, in Hz.
28   min-freq:
31       Minimum DDR clock frequency for the speed-bin, in Hz.
47       Four-bank activate window in pico seconds.
54   tR2R-C2C:
57       Additional READ-to-READ delay in chip-to-chip cases in pico seconds.
67       ACTIVATE-to-ACTIVATE command period in pico seconds.
72       RAS-to-CAS delay in pico seconds.
99   tW2W-C2C:
102       Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.
112       Internal WRITE-to-READ command delay in pico seconds.
117       Exit power-down to next valid command delay in pico seconds.
125   - compatible
126   - min-freq
127   - max-freq
132   - |
135             compatible = "jedec,lpddr3-timings";
136             max-freq = <800000000>;
137             min-freq = <100000000>;
142             tR2R-C2C = <0>;
151             tW2W-C2C = <0>;