memory-controllers/ddr/jedec%2Clpddr2.yaml

53       Active bank a to active bank b in terms of number of clock cycles.
60       Internal WRITE-to-READ command delay in terms of number of clock cycles.
67       Exit power-down to next valid command delay in terms of number of clock
74       Internal READ to PRECHARGE command delay in terms of number of clock
81       CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
88       Row precharge time (all banks) in terms of number of clock cycles.
95       RAS-to-CAS delay in terms of number of clock cycles. Obtained from
102       WRITE recovery time in terms of number of clock cycles. Obtained from
109       Row active time in terms of number of clock cycles. Obtained from device
117       SELF REFRESH) in terms of number of clock cycles. Obtained from device
124       Four-bank activate window in terms of number of clock cycles. Obtained