memory-controllers/ddr/jedec%2Clpddr2-timings.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10   - Krzysztof Kozlowski <krzk@kernel.org>
14     const: jedec,lpddr2-timings
16   max-freq:
19       Maximum DDR clock frequency for the speed-bin, in Hz.
21   min-freq:
24       Minimum DDR clock frequency for the speed-bin, in Hz.
32   tDQSCK-max:
37   tDQSCK-max-derated:
40       DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
46       Four-bank activate window in pico seconds.
48   tRAS-max-ns:
52   tRAS-min:
60       RAS-to-CAS delay in pico seconds.
85       Internal WRITE-to-READ command delay in pico seconds.
90       Exit power-down to next valid command delay in pico seconds.
108   - compatible
109   - min-freq
110   - max-freq
115   - |
117         compatible = "jedec,lpddr2-timings";
118         min-freq = <10000000>;
119         max-freq = <400000000>;
121         tDQSCK-max = <5500>;
123         tRAS-max-ns = <70000>;
124         tRAS-min = <42000>;