memory-controllers/ddr/jedec%2Clpddr-channel.yaml

4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
7 title: LPDDR channel with chip/rank topology description
10   An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
11   CK, etc.) that connect one or more LPDDR chips to a host system. The main
12   purpose of this node is to overall LPDDR topology of the system, including the
13   amount of individual LPDDR chips and the ranks per chip.
29       from (a multiple of) the io-width of the LPDDR chip, that means that
35       connected LPDDR chip, times the io-width of the channel divided by
36       the io-width of the LPDDR chip.
54       Each physical LPDDR chip may have one or more ranks. Ranks are
55       internal but fully independent sub-units of the chip. Each LPDDR bus
110     lpddr-channel0 {
125     lpddr-channel1 {