bindings/media/qcom%2Csdm845-camss.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   - Robert Foss <robert.foss@linaro.org>
18     const: qcom,sdm845-camss
24   clock-names:
26       - const: camnoc_axi
27       - const: cpas_ahb
28       - const: cphy_rx_src
29       - const: csi0
30       - const: csi0_src
31       - const: csi1
32       - const: csi1_src
33       - const: csi2
34       - const: csi2_src
35       - const: csiphy0
36       - const: csiphy0_timer
37       - const: csiphy0_timer_src
38       - const: csiphy1
39       - const: csiphy1_timer
40       - const: csiphy1_timer_src
41       - const: csiphy2
42       - const: csiphy2_timer
43       - const: csiphy2_timer_src
44       - const: csiphy3
45       - const: csiphy3_timer
46       - const: csiphy3_timer_src
47       - const: gcc_camera_ahb
48       - const: gcc_camera_axi
49       - const: slow_ahb_src
50       - const: soc_ahb
51       - const: vfe0_axi
52       - const: vfe0
53       - const: vfe0_cphy_rx
54       - const: vfe0_src
55       - const: vfe1_axi
56       - const: vfe1
57       - const: vfe1_cphy_rx
58       - const: vfe1_src
59       - const: vfe_lite
60       - const: vfe_lite_cphy_rx
61       - const: vfe_lite_src
67   interrupt-names:
69       - const: csid0
70       - const: csid1
71       - const: csid2
72       - const: csiphy0
73       - const: csiphy1
74       - const: csiphy2
75       - const: csiphy3
76       - const: vfe0
77       - const: vfe1
78       - const: vfe_lite
83   power-domains:
85       - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
86       - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
87       - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
97         $ref: /schemas/graph.yaml#/$defs/port-base
104             $ref: video-interfaces.yaml#
108               data-lanes:
113               - data-lanes
116         $ref: /schemas/graph.yaml#/$defs/port-base
123             $ref: video-interfaces.yaml#
127               data-lanes:
132               - data-lanes
135         $ref: /schemas/graph.yaml#/$defs/port-base
142             $ref: video-interfaces.yaml#
146               data-lanes:
151               - data-lanes
154         $ref: /schemas/graph.yaml#/$defs/port-base
161             $ref: video-interfaces.yaml#
165               data-lanes:
170               - data-lanes
176   reg-names:
178       - const: csid0
179       - const: csid1
180       - const: csid2
181       - const: csiphy0
182       - const: csiphy1
183       - const: csiphy2
184       - const: csiphy3
185       - const: vfe0
186       - const: vfe1
187       - const: vfe_lite
189   vdda-phy-supply:
191       Phandle to a regulator supply to PHY core block.
193   vdda-pll-supply:
195       Phandle to 1.8V regulator supply to PHY refclk pll block.
198   - clock-names
199   - clocks
200   - compatible
201   - interrupt-names
202   - interrupts
203   - iommus
204   - power-domains
205   - reg
206   - reg-names
207   - vdda-phy-supply
208   - vdda-pll-supply
213   - |
214     #include <dt-bindings/interrupt-controller/arm-gic.h>
215     #include <dt-bindings/clock/qcom,camcc-sdm845.h>
216     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
219       #address-cells = <2>;
220       #size-cells = <2>;
223         compatible = "qcom,sdm845-camss";
262         clock-names = "camnoc_axi",
310         interrupt-names = "csid0",
326         power-domains = <&clock_camcc IFE_0_GDSC>,
341         reg-names = "csid0",
352         vdda-phy-supply = <&vreg_l1a_0p875>;
353         vdda-pll-supply = <&vreg_l26a_1p2>;
356           #address-cells = <1>;
357           #size-cells = <0>;