bindings/media/mediatek%2Cmdp3-tcc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Matthias Brugger <matthias.bgg@gmail.com>
21       - mediatek,mt8195-mdp3-tcc
26   mediatek,gce-client-reg:
28       The register of display function block to be set by gce. There are 4 arguments,
29       such as gce node, subsys id, offset and register size. The subsys id that is
30       mapping to the register of display function blocks is defined in the gce header
31       include/dt-bindings/gce/<chip>-gce.h of each chips.
32     $ref: /schemas/types.yaml#/definitions/phandle-array
35         - description: phandle of GCE
36         - description: GCE subsys id
37         - description: register offset
38         - description: register size
45   - compatible
46   - reg
47   - mediatek,gce-client-reg
48   - clocks
53   - |
54     #include <dt-bindings/clock/mt8195-clk.h>
55     #include <dt-bindings/gce/mt8195-gce.h>
58         compatible = "mediatek,mt8195-mdp3-tcc";
60         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;