Lines Matching +full:per +full:- +full:port
1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
5 The TDA19971 Video port output pins can be used as follows:
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
15 The TDA19973 Video port output pins can be used as follows:
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
17 - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
18 - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
19 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
21 The Video port output pins are mapped via 4-bit 'pin groups' allowing
23 pin groups. The video_portcfg device-tree property consists of register mapping
24 pairs which map a chip-specific VP output register to a 4-bit pin group. If
25 the pin group needs to be bit-swapped you can use the *_S pin-group defines.
28 - compatible :
29 - "nxp,tda19971" for the TDA19971
30 - "nxp,tda19973" for the TDA19973
31 - reg : I2C slave address
32 - interrupts : The interrupt number
33 - DOVDD-supply : Digital I/O supply
34 - DVDD-supply : Digital Core supply
35 - AVDD-supply : Analog supply
36 - nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups.
39 - nxp,audout-format : DAI bus format: "i2s" or "spdif".
40 - nxp,audout-width : width of audio output data bus (1-4).
41 - nxp,audout-layout : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used).
42 - nxp,audout-mclk-fs : Multiplication factor between stream rate and codec
45 The port node shall contain one endpoint child node for its digital
46 output video port, in accordance with the video interface bindings defined in
47 Documentation/devicetree/bindings/media/video-interfaces.txt.
50 The following three properties are defined in video-interfaces.txt and
52 - hsync-active: Horizontal synchronization polarity. Defaults to active high.
53 - vsync-active: Vertical synchronization polarity. Defaults to active high.
54 - data-active: Data polarity. Defaults to active high.
57 - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422
59 hdmi-receiver@48 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_tda1997x>;
64 interrupt-parent = <&gpio1>;
66 DOVDD-supply = <®_3p3v>;
67 AVDD-supply = <®_1p8v>;
68 DVDD-supply = <®_1p8v>;
70 #sound-dai-cells = <0>;
71 nxp,audout-format = "i2s";
72 nxp,audout-layout = <0>;
73 nxp,audout-width = <16>;
74 nxp,audout-mclk-fs = <128>;
76 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
79 nxp,vidout-portcfg =
80 /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
82 /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
84 /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
86 /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
89 port {
91 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
92 bus-width = <16>;
93 hsync-active = <1>;
94 vsync-active = <1>;
95 data-active = <1>;
99 - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
101 hdmi-receiver@48 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_tda1997x>;
106 interrupt-parent = <&gpio1>;
108 DOVDD-supply = <®_3p3v>;
109 AVDD-supply = <®_1p8v>;
110 DVDD-supply = <®_1p8v>;
112 #sound-dai-cells = <0>;
113 nxp,audout-format = "i2s";
114 nxp,audout-layout = <0>;
115 nxp,audout-width = <16>;
116 nxp,audout-mclk-fs = <128>;
118 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
121 nxp,vidout-portcfg =
122 /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
124 /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
126 /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
128 /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
131 port {
133 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
134 bus-width = <16>;
135 hsync-active = <1>;
136 vsync-active = <1>;
137 data-active = <1>;
141 - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
143 hdmi-receiver@48 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_tda1997x>;
148 interrupt-parent = <&gpio1>;
150 DOVDD-supply = <®_3p3v>;
151 AVDD-supply = <®_1p8v>;
152 DVDD-supply = <®_1p8v>;
154 #sound-dai-cells = <0>;
155 nxp,audout-format = "i2s";
156 nxp,audout-layout = <0>;
157 nxp,audout-width = <16>;
158 nxp,audout-mclk-fs = <128>;
163 nxp,vidout-portcfg =
164 /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
166 /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
169 port {
171 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
172 bus-width = <16>;
173 hsync-active = <1>;
174 vsync-active = <1>;
175 data-active = <1>;