media/i2c/tda1997x.txt

10  - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
13  - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16  - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
17  - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
18  - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
19  - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
22 for a variety of connection possibilities including swapping pin order within
24 pairs which map a chip-specific VP output register to a 4-bit pin group. If
58    16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
80 			/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
82 			/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
99  - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
100    16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
122 			/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
124 			/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
141  - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
142    16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
164 			/* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
166 			/* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */