Lines Matching +full:al5d +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
23 - items:
24 - const: allegro,al5e-1.1
25 - const: allegro,al5e
26 - items:
27 - const: allegro,al5d-1.1
28 - const: allegro,al5d
32 - description: The registers
33 - description: The SRAM
35 reg-names:
37 - const: regs
38 - const: sram
41 maxItems: 1
45 - description: Core clock
46 - description: MCU clock
47 - description: Core AXI master port clock
48 - description: MCU AXI master port clock
49 - description: AXI4-Lite slave port clock
51 clock-names:
53 - const: core_clk
54 - const: mcu_clk
55 - const: m_axi_core_aclk
56 - const: m_axi_mcu_aclk
57 - const: s_axi_lite_aclk
60 - compatible
61 - reg
62 - reg-names
63 - interrupts
64 - clocks
65 - clock-names
70 - |
72 #address-cells = <2>;
73 #size-cells = <2>;
75 al5e: video-codec@a0009000 {
76 compatible = "allegro,al5e-1.1", "allegro,al5e";
79 reg-names = "regs", "sram";
81 clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>,
83 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
87 - |
89 #address-cells = <2>;
90 #size-cells = <2>;
92 al5d: video-codec@a0029000 {
93 compatible = "allegro,al5d-1.1", "allegro,al5d";
96 reg-names = "regs", "sram";
100 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",