Lines Matching full:smmu
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
18 The SMMU may also raise interrupts in response to various fault
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
38 - qcom,qcm2290-smmu-500
39 - qcom,qcs8300-smmu-500
40 - qcom,qdu1000-smmu-500
41 - qcom,sa8255p-smmu-500
42 - qcom,sa8775p-smmu-500
43 - qcom,sc7180-smmu-500
44 - qcom,sc7280-smmu-500
45 - qcom,sc8180x-smmu-500
46 - qcom,sc8280xp-smmu-500
47 - qcom,sdm670-smmu-500
48 - qcom,sdm845-smmu-500
49 - qcom,sdx55-smmu-500
50 - qcom,sdx65-smmu-500
51 - qcom,sdx75-smmu-500
52 - qcom,sm6115-smmu-500
53 - qcom,sm6125-smmu-500
54 - qcom,sm6350-smmu-500
55 - qcom,sm6375-smmu-500
56 - qcom,sm8150-smmu-500
57 - qcom,sm8250-smmu-500
58 - qcom,sm8350-smmu-500
59 - qcom,sm8450-smmu-500
60 - qcom,sm8550-smmu-500
61 - qcom,sm8650-smmu-500
62 - qcom,x1e80100-smmu-500
63 - const: qcom,smmu-500
71 - qcom,qcm2290-smmu-500
72 - qcom,sc7180-smmu-500
73 - qcom,sc7280-smmu-500
74 - qcom,sc8180x-smmu-500
75 - qcom,sc8280xp-smmu-500
76 - qcom,sdm845-smmu-500
77 - qcom,sm6115-smmu-500
78 - qcom,sm6350-smmu-500
79 - qcom,sm6375-smmu-500
80 - qcom,sm8150-smmu-500
81 - qcom,sm8250-smmu-500
82 - qcom,sm8350-smmu-500
83 - qcom,sm8450-smmu-500
85 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
88 - qcom,qcm2290-smmu-500
89 - qcom,sa8255p-smmu-500
90 - qcom,sa8775p-smmu-500
91 - qcom,sc7280-smmu-500
92 - qcom,sc8180x-smmu-500
93 - qcom,sc8280xp-smmu-500
94 - qcom,sm6115-smmu-500
95 - qcom,sm6125-smmu-500
96 - qcom,sm8150-smmu-500
97 - qcom,sm8250-smmu-500
98 - qcom,sm8350-smmu-500
99 - qcom,sm8450-smmu-500
100 - qcom,sm8550-smmu-500
101 - qcom,sm8650-smmu-500
102 - qcom,x1e80100-smmu-500
103 - const: qcom,adreno-smmu
104 - const: qcom,smmu-500
111 - qcom,sc7280-smmu-500
112 - qcom,sm8150-smmu-500
113 - qcom,sm8250-smmu-500
114 - const: qcom,adreno-smmu
116 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
119 - qcom,msm8996-smmu-v2
120 - qcom,sc7180-smmu-v2
121 - qcom,sdm630-smmu-v2
122 - qcom,sdm845-smmu-v2
123 - qcom,sm6350-smmu-v2
124 - qcom,sm7150-smmu-v2
125 - const: qcom,adreno-smmu
126 - const: qcom,smmu-v2
129 - const: qcom,sdm845-smmu-v2
130 - const: qcom,smmu-v2
133 - const: marvell,ap806-smmu-500
141 - nvidia,tegra186-smmu
142 - nvidia,tegra194-smmu
143 - nvidia,tegra234-smmu
144 - const: nvidia,smmu-500
147 - const: arm,smmu-v2
152 - const: arm,smmu-v1
154 - arm,smmu-v1
155 - arm,smmu-v2
159 - cavium,smmu-v2
176 by that device into the relevant SMMU.
189 interrupts, specified in order of their indexing by the SMMU.
197 Present if page table walks made by the SMMU are cache coherent with the
200 NOTE: this only applies to the SMMU itself, not masters connected
201 upstream of the SMMU.
203 calxeda,smmu-secure-config-access:
207 access to SMMU configuration registers. In this case non-secure aliases of
208 secure registers have to be used during SMMU configuration.
238 client IDs to ARM SMMU stream IDs.
260 - nvidia,tegra186-smmu
261 - nvidia,tegra194-smmu
262 - nvidia,tegra234-smmu
284 - qcom,msm8998-smmu-v2
285 - qcom,sdm630-smmu-v2
295 the smmu ptw
304 - description: interface clock required to access smmu's registers
312 - const: iface-smmu
313 - const: bus-smmu
318 - description: interface clock required to access smmu's registers
320 - description: bus clock required for the smmu ptw
327 - qcom,sm6375-smmu-v2
337 the smmu ptw
346 - description: interface clock required to access smmu's registers
354 - const: iface-smmu
356 - const: bus-smmu
361 - description: interface clock required to access smmu's registers
364 - description: bus clock required for the smmu ptw
371 - qcom,msm8996-smmu-v2
372 - qcom,sc7180-smmu-v2
373 - qcom,sdm845-smmu-v2
384 the smmu ptw
385 - description: interface clock required to access smmu's registers
393 - qcom,sa8775p-smmu-500
394 - qcom,sc7280-smmu-500
395 - qcom,sc8280xp-smmu-500
413 - description: GPU hlos1_vote_GPU smmu clock
423 - qcom,sc8180x-smmu-500
424 - qcom,sm6350-smmu-v2
425 - qcom,sm7150-smmu-v2
426 - qcom,sm8150-smmu-500
427 - qcom,sm8250-smmu-500
440 the smmu ptw
441 - description: interface clock required to access smmu's registers
449 - qcom,sm8350-smmu-500
450 - const: qcom,adreno-smmu
451 - const: qcom,smmu-500
473 - qcom,qcm2290-smmu-500
474 - qcom,sm6115-smmu-500
475 - qcom,sm6125-smmu-500
476 - const: qcom,adreno-smmu
477 - const: qcom,smmu-500
490 - description: Voter clock required for HLOS SMMU access
497 - const: qcom,sm8450-smmu-500
498 - const: qcom,adreno-smmu
499 - const: qcom,smmu-500
527 - qcom,sm8550-smmu-500
528 - qcom,sm8650-smmu-500
529 - qcom,x1e80100-smmu-500
530 - const: qcom,adreno-smmu
531 - const: qcom,smmu-500
555 - cavium,smmu-v2
556 - marvell,ap806-smmu-500
557 - nvidia,smmu-500
558 - qcom,qcs8300-smmu-500
559 - qcom,qdu1000-smmu-500
560 - qcom,sa8255p-smmu-500
561 - qcom,sc7180-smmu-500
562 - qcom,sdm670-smmu-500
563 - qcom,sdm845-smmu-500
564 - qcom,sdx55-smmu-500
565 - qcom,sdx65-smmu-500
566 - qcom,sm6350-smmu-500
567 - qcom,sm6375-smmu-500
577 const: qcom,sm6375-smmu-500
595 /* SMMU with stream matching or stream indexing */
597 compatible = "arm,smmu-v1";
616 /* SMMU with stream matching */
618 compatible = "arm,smmu-v1";
644 compatible = "arm,mmu-500", "arm,smmu-v2";
660 ID each, but may master through multiple SMMU TBUs */
667 /* Qcom's arm,smmu-v2 implementation */
671 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";