Lines Matching +full:1 +full:v2
15 Management Unit Architecture, which can be used to provide 1 or 2 stages
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
116 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
119 - qcom,msm8996-smmu-v2
120 - qcom,sc7180-smmu-v2
121 - qcom,sdm630-smmu-v2
122 - qcom,sdm845-smmu-v2
123 - qcom,sm6350-smmu-v2
124 - qcom,sm7150-smmu-v2
126 - const: qcom,smmu-v2
129 - const: qcom,sdm845-smmu-v2
130 - const: qcom,smmu-v2
147 - const: arm,smmu-v2
155 - arm,smmu-v2
159 - cavium,smmu-v2
162 minItems: 1
172 enum: [ 1, 2 ]
175 value of 1, each IOMMU specifier represents a distinct stream ID emitted
184 minItems: 1
213 For SMMUs supporting stream matching and using #iommu-cells = <1>,
223 minItems: 1
227 minItems: 1
231 minItems: 1
266 minItems: 1
277 maxItems: 1
284 - qcom,msm8998-smmu-v2
285 - qcom,sdm630-smmu-v2
327 - qcom,sm6375-smmu-v2
371 - qcom,msm8996-smmu-v2
372 - qcom,sc7180-smmu-v2
373 - qcom,sdm845-smmu-v2
424 - qcom,sm6350-smmu-v2
425 - qcom,sm7150-smmu-v2
555 - cavium,smmu-v2
591 maxItems: 1
606 #iommu-cells = <1>;
636 /* device with stream IDs 1, 17, 33 and 49 */
638 iommus = <&smmu2 1 0x30>;
644 compatible = "arm,mmu-500", "arm,smmu-v2";
653 #iommu-cells = <1>;
667 /* Qcom's arm,smmu-v2 implementation */
671 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
674 #global-interrupts = <1>;
678 #iommu-cells = <1>;