bindings/interrupt-controller/riscv%2Cimsics.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10   - Anup Patel <anup@brainfault.org>
13   The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14   MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15   AIA specification can be found at https://github.com/riscv/riscv-aia.
17   The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
18   for each privilege level (machine or supervisor). The configuration of
22   which is same for given privilege level across CPUs (or HARTs).
24   The device tree of a RISC-V platform will have one IMSIC device tree node
25   for each privilege level (machine or supervisor) which collectively describe
26   IMSIC interrupt files at that privilege level across CPUs (or HARTs).
28   The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform
29   follows a particular scheme defined by the RISC-V AIA specification. A IMSIC
30   group is a set of IMSIC interrupt files co-located in MMIO space and we can
32   RISC-V platform. The MSI target address of a IMSIC interrupt file at given
33   privilege level (machine or supervisor) encodes group index, HART index,
36   XLEN-1            > (HART Index MSB)                  12    0
38   -------------------------------------------------------------
40   -------------------------------------------------------------
43   - $ref: /schemas/interrupt-controller.yaml#
44   - $ref: /schemas/interrupt-controller/msi-controller.yaml#
49       - enum:
50           - qemu,imsics
51       - const: riscv,imsics
59   interrupt-controller: true
61   "#interrupt-cells":
64   msi-controller: true
66   "#msi-cells":
69   interrupts-extended:
75       to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V
78   riscv,num-ids:
85   riscv,num-guest-ids:
92       riscv,num-ids property.
94   riscv,guest-index-bits:
101   riscv,hart-index-bits:
106       specified it is calculated based on the interrupts-extended property.
108   riscv,group-index-bits:
115   riscv,group-index-shift:
125   - compatible
126   - reg
127   - interrupt-controller
128   - msi-controller
129   - "#msi-cells"
130   - interrupts-extended
131   - riscv,num-ids
136   - |
137     // Example 1 (Machine-level IMSIC files with just one group):
139     interrupt-controller@24000000 {
141       interrupts-extended = <&cpu1_intc 11>,
146       interrupt-controller;
147       #interrupt-cells = <0>;
148       msi-controller;
149       #msi-cells = <0>;
150       riscv,num-ids = <127>;
153   - |
154     // Example 2 (Supervisor-level IMSIC files with two groups):
156     interrupt-controller@28000000 {
158       interrupts-extended = <&cpu1_intc 9>,
164       interrupt-controller;
165       #interrupt-cells = <0>;
166       msi-controller;
167       #msi-cells = <0>;
168       riscv,num-ids = <127>;
169       riscv,group-index-bits = <1>;
170       riscv,group-index-shift = <24>;